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Commit 4ceaf67e authored by George Hotz's avatar George Hotz
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remove mtc0

parent 57a15673
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mipsevm/test/bds_mtc0.asm deleted 100644 → 0
View file @ 57a15673
###############################################################################
# File : bds_mtc0.asm
# Project : MIPS32 MUX
# Author: : Grant Ayers (ayers@cs.stanford.edu)
#
# Standards/Formatting:
# MIPS gas, soft tab, 80 column
#
# Description:
# Test the functionality of the 'mtc0' instruction in a branch delay slot
#
###############################################################################
.section .test, "x"
.balign 4
.set noreorder
.global test
.ent test
test:
lui $s0, 0xbfff # Load the base address 0xbffffff0
ori $s0, 0xfff0
ori $s1, $0, 1 # Prepare the 'done' status
#### Test code start ####
lui $t0, 0xc001
ori $t0, 0xcafe
j $check
mtc0 $t0, $11, 0
j $end
move $v0, $0
$check:
mfc0 $t1, $11, 0
subu $t2, $t0, $t1
sltiu $v0, $t2, 1
$end:
#### Test code end ####
sw $v0, 8($s0) # Set the test result
sw $s1, 4($s0) # Set 'done'
$done:
jr $ra
nop
.end test
mipsevm/test/interrupt_sw.asm deleted 100644 → 0
View file @ 57a15673
###############################################################################
# File : interrupt_sw.asm
# Project : MIPS32 MUX
# Author: : Grant Ayers (ayers@cs.stanford.edu)
#
# Standards/Formatting:
# MIPS gas, soft tab, 80 column
#
# Description:
# Test the basic functionality of software interrupts.
# This triggers SW Int 0 to the general exception vector (0x80000180)
# and then SW Int 1 to the interrupt vector (0x80000200), thus
# performing basic verification of the exception vectors and offsets too.
#
###############################################################################
.section .test, "x"
.balign 4
.set noreorder
.global test
.ent test
test:
lui $s0, 0xbfff # Load the base address 0xbffffff0
ori $s0, 0xfff0
ori $s1, $0, 1 # Prepare the 'done' status
#### Test code start ####
j $setup # Enable interrupts and exit boot mode
nop
$run:
move $s2, $ra # Save $ra since we'll use it
sw $0, 12($s0) # Clear the scratch register
mfc0 $k0, $13, 0 # Fire sw interrupt 0 to 0x80000180 (general)
ori $k0, 0x0100
mtc0 $k0, $13, 0
jal busy
nop
lw $t0, 12($s0) # Check scratch register for 0x1
addiu $t1, $t0, -1
bne $t1, $0, $fail
nop
mfc0 $k0, $13, 0
lui $t2, 0x0080 # Enable the 'special' interrupt vector
ori $t2, 0x0200 # Fire sw interrupt 1 to 0x80000200 (iv)
or $k1, $k0, $t2
mtc0 $k1, $13, 0
jal busy
nop
lw $t3, 12($s0) # Check scratch register for 0x2
addiu $t4, $t3, -2
bne $t4, $0, $fail
nop
sw $s1, 8($s0) # Set the test to pass
sw $s1, 4($s0) # Set 'done'
jr $s2
$fail:
sw $0, 8($s0) # Set the test result
sw $s1, 4($s0) # Set 'done'
jr $s2
$setup:
mfc0 $k0, $12, 0 # Load the Status register
lui $k1, 0x1000 # Allow access to CP0
ori $k1, 0x0301 # Enable sw Int 0,1
or $k0, $k0, $k1
lui $k1, 0x1dbf # Disable CP3-1, No RE, No BEV
ori $k1, 0x03e7 # Disable hw ints, sw int 1-0, kernel mode, IE
and $k0, $k0, $k1
mtc0 $k0, $12, 0 # Commit the new Status register
la $k0, $run # Set ErrorEPC address to main test body
mtc0 $k0, $30, 0
eret
busy: # Allow time for an interrupt to be detected
nop
nop
nop
nop
nop
nop
nop
nop
nop
jr $ra
nop
#### Test code end ####
.end test
mipsevm/test/interrupt_timer.asm deleted 100644 → 0
View file @ 57a15673
###############################################################################
# File : int_timer_cache.asm
# Project : MIPS32 MUX
# Author: : Grant Ayers (ayers@cs.stanford.edu)
#
# Standards/Formatting:
# MIPS gas, soft tab, 80 column
#
# Description:
# Test the timer interrupt, i.e., hardware interrupt 5 with the interrupt
# vector running from the cache
#
###############################################################################
.section .test, "x"
.balign 4
.set noreorder
.global test
.ent test
test:
lui $s0, 0xbfff # Load the base address 0xbffffff0
ori $s0, 0xfff0
ori $s1, $0, 1 # Prepare the 'done' status
#### Test code start ####
j $setup # Enable interrupts and exit boot mode
nop
$run:
lw $t0, 0($a0) # Return success if the counter is >=30
sltiu $t1, $t0, 30
bne $t1, $0, $run
nop
sw $s1, 8($s0)
sw $s1, 4($s0)
$loop:
j $loop
nop
$setup:
mfc0 $k0, $16, 0 # Config: Enable kseg0 caching
lui $k1, 0xffff
ori $k1, 0xfff8
and $k0, $k0, $k1
ori $k0, 0x3
mtc0 $k0, $16, 0
mfc0 $k0, $12, 0 # Status: CP0, timer (int 5), ~CP3-1, ~RE, ~BEV, kernel, IE
lui $k1, 0x1dbf
ori $k1, 0x80e7
and $k0, $k0, $k1
lui $k1, 0x1000
ori $k1, 0x8001
or $k0, $k0, $k1
mtc0 $k0, $12, 0
mfc0 $k0, $13, 0 # Cause: Use the special interrupt vector
lui $k1, 0x0080
or $k0, $k0, $k1
mtc0 $k0, $13, 0
mfc0 $k0, $9, 0 # Set Compare to the near future (+200 cycles)
addiu $k0, 200
mtc0 $k0, $11, 0
la $k0, $run # Set ErrorEPC address to main test body (cached)
lui $k1, 0xdfff
ori $k1, 0xffff
and $k0, $k0, $k1
mtc0 $k0, $30, 0
la $a0, data # Use $a0 to hold the address of the iteration count
eret
data:
.word 0x0
#### Test code end ####
.end test
mipsevm/test/llsc.asm deleted 100644 → 0
View file @ 57a15673
###############################################################################
# File : llsc.asm
# Project : MIPS32 MUX
# Author: : Grant Ayers (ayers@cs.stanford.edu)
#
# Standards/Formatting:
# MIPS gas, soft tab, 80 column
#
# Description:
# Test the functionality of the 'll' and 'sc' instructions.
#
###############################################################################
.section .test, "x"
.balign 4
.set noreorder
.global test
.ent test
test:
lui $s0, 0xbfff # Load the base address 0xbffffff0
ori $s0, 0xfff0
ori $s1, $0, 1 # Prepare the 'done' status
#### Test code start ####
lui $s2, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting
ori $s2, 0x07fc # from 0xbfc00000)
lui $s3, 0xdeaf # Original memory word: 0xdeafbeef
ori $s3, 0xbeef
sw $s3, 0($s2)
lui $s4, 0xc001 # New memory word: 0xc001cafe
ori $s4, 0xcafe
### Test: Success
move $t0, $s3
move $t1, $s4
ll $t2, 0($s2)
sc $t1, 0($s2)
subu $v1, $t2, $s3 # Make sure the load worked
sltiu $v0, $v1, 1
lw $t3, 0($s2) # Memory should have the new value
subu $v1, $t3, $s4
sltiu $v1, $v1, 1
and $v0, $v0, $v1
addiu $v1, $t1, -1 # The sc dest reg should be 1
sltiu $v1, $v1, 1
and $v0, $v0, $v1
### Test: Failure
move $t4, $s4
sw $s3, 0($s2)
ll $t5, 0($s2)
sw $0, 0($s2)
sc $t4, 0($s2)
subu $v1, $t5, $s3 # Make sure the loads worked
sltiu $v1, $v1, 1
and $v0, $v0, $v1
lw $t7, 0($s2) # Memory should have the old value
sltiu $v1, $t7, 1
and $v0, $v0, $v1
sltiu $v1, $t4, 1 # The sc dest reg should be 0
and $v0, $v0, $v1
### Test: Failure (Eret)
sw $s3, 0($s2)
move $t8, $s4
mfc0 $k0, $12, 0 # Load the Status register
lui $k1, 0x1dbf # Disable CP1-3, No RE, No BEV
ori $k1, 0x00e6 # Disable ints, kernel mode
and $k0, $k0, $k1
mtc0 $k0, $12, 0
la $k1, $post_eret
mtc0 $k1, $30, 0
ll $t9, 0($s2)
eret
$post_eret:
sc $t8, 0($s2)
subu $v1, $t9, $s3 # Make sure the load worked
sltiu $v1, $v1, 1
and $v0, $v0, $v1
lw $s5, 0($s2) # Memory should have the old value
subu $v1, $s5, $s3
sltiu $v1, $v1, 1
and $v0, $v0, $v1
sltiu $v1, $t8, 1 # The sc dest reg should be 0
and $v0, $v0, $v1
#### Test code end ####
sw $v0, 8($s0) # Set the test result
sw $s1, 4($s0) # Set 'done'
$done:
jr $ra
nop
.end test
mipsevm/test/mftc0.asm deleted 100644 → 0
View file @ 57a15673
###############################################################################
# File : mftc0.asm
# Project : MIPS32 MUX
# Author: : Grant Ayers (ayers@cs.stanford.edu)
#
# Standards/Formatting:
# MIPS gas, soft tab, 80 column
#
# Description:
# Test the functionality of the 'mfc0' and 'mtc0' instructions.
#
###############################################################################
.section .test, "x"
.balign 4
.set noreorder
.global test
.ent test
test:
lui $s0, 0xbfff # Load the base address 0xbffffff0
ori $s0, 0xfff0
ori $s1, $0, 1 # Prepare the 'done' status
#### Test code start ####
# Read and set the compare register (Reg 11 Sel 0)
lui $t0, 0xc001
ori $t0, 0xcafe
mtc0 $t0, $11, 0
mfc0 $t1, $11, 0
subu $t2, $t0, $t1
sltiu $v0, $t2, 1
# TODO: Add more tests
#### Test code end ####
sw $v0, 8($s0) # Set the test result
sw $s1, 4($s0) # Set 'done'
$done:
jr $ra
nop
.end test
mipsevm/test/tlbwirp.asm deleted 100644 → 0
View file @ 57a15673
###############################################################################
# File : tlbwirp.asm
# Project : MIPS32 MUX
# Author: : Grant Ayers (ayers@cs.stanford.edu)
#
# Standards/Formatting:
# MIPS gas, soft tab, 80 column
#
# Description:
# Test the functionality of the 'tlbwi' 'tlbr' and 'tlbp' instructions.
#
###############################################################################
.section .test, "x"
.balign 4
.set noreorder
.global test
.ent test
test:
lui $s0, 0xbfff # Load the base address 0xbffffff0
ori $s0, 0xfff0
ori $s1, $0, 1 # Prepare the 'done' status
#### Test code start ####
ori $t0, $0, 4 # Reserve (wire) 3 TLB entries
mtc0 $t0, $6, 0
ori $t1, $0, 2 # Set the TLB index to 2 (third entry)
mtc0 $t1, $0, 0
lui $t2, 0x0200 # Set the PFN to 2GB, cacheable, dirty, valid,
ori $t2, 0x003f # for EntryLo0/EntryLo1
mtc0 $t2, $2, 0
mtc0 $t2, $3, 0
lui $t3, 0x0001 # Set the page size to 64KB (0xf) in PageMask
ori $t3, 0xe000
mtc0 $t3, $5, 0
ori $t4, $0, 100 # Set VPN2 to map the first 64-KiB page. Set ASID to 100
mtc0 $t4, $10, 0
tlbwi # Write Index
mtc0 $0, $2, 0 # Clear EntryLo0,EntryLo1,EntryHi,PageMask
mtc0 $0, $3, 0
mtc0 $0, $5, 0
mtc0 $0, $10, 0
tlbr # Read TLB index 2
mfc0 $s2, $2, 0 # (EntryLo0)
mfc0 $s3, $3, 0 # (EntryLo1)
mfc0 $s4, $5, 0 # (PageMask)
mfc0 $s5, $10, 0 # (EntryHi)
subu $v1, $t2, $s2 # Validate read
sltiu $v0, $v1, 1
subu $v1, $t2, $s3
sltiu $v1, $v1, 1
and $v0, $v0, $v1
subu $v1, $t3, $s4
sltiu $v1, $v1, 1
and $v0, $v0, $v1
subu $v1, $t4, $s5
sltiu $v1, $v1, 1
and $v0, $v0, $v1
mtc0 $0, $0, 0 # Clear Index for tlbp
tlbp
mfc0 $s6, $0, 0 # (Index)
subu $v1, $t1, $s6 # Verify tlbp hit
sltiu $v1, $v1, 1
and $v0, $v0, $v1
lui $t5, 0xffff # Set a bogus value to EntryHi
ori $t5, 0xffff
mtc0 $t5, $10, 0
tlbp
lui $t6, 0x8000 # Verify tlbp miss
mfc0 $s7, $10, 0
and $s7, $s7, $t6
subu $v1, $t6, $s7
sltiu $v1, $v1, 1
and $v0, $v0, $v1
#### Test code end ####
sw $v0, 8($s0) # Set the test result
sw $s1, 4($s0) # Set 'done'
$done:
jr $ra
nop
.end test
mipsevm/test/tlbwrrp.asm deleted 100644 → 0
View file @ 57a15673
###############################################################################
# File : tlbwr.asm
# Project : MIPS32 MUX
# Author: : Grant Ayers (ayers@cs.stanford.edu)
#
# Standards/Formatting:
# MIPS gas, soft tab, 80 column
#
# Description:
# Test the functionality of the 'tlbwr' 'tlbr' and 'tlbp' instructions.
#
###############################################################################
.section .test, "x"
.balign 4
.set noreorder
.global test
.ent test
test:
lui $s0, 0xbfff # Load the base address 0xbffffff0
ori $s0, 0xfff0
ori $s1, $0, 1 # Prepare the 'done' status
#### Test code start ####
ori $t0, $0, 8 # Reserve (wire) 8 TLB entries
mtc0 $t0, $6, 0
ori $t1, $0, 3 # Set the TLB index to 2 (third entry)
mtc0 $t1, $0, 0
lui $t2, 0x0200 # Set the PFN to 2GB, cacheable, dirty, valid,
ori $t2, 0x003f # for EntryLo0/EntryLo1
mtc0 $t2, $2, 0
mtc0 $t2, $3, 0
lui $t3, 0x0001 # Set the page size to 64KB (0xf) in PageMask
ori $t3, 0xe000
mtc0 $t3, $5, 0
ori $t4, $0, 100 # Set VPN2 to map the first 64-KiB page. Set ASID to 100
mtc0 $t4, $10, 0
tlbwr # Write Random
mtc0 $0, $2, 0 # Clear EntryLo0,EntryLo1,PageMask
mtc0 $0, $3, 0
mtc0 $0, $5, 0
tlbp # Verify TLB hit
mfc0 $s2, $0, 0
srl $v1, $s2, 31
sltiu $v0, $v1, 1
sltiu $v1, $s2, 16 # Verify index is in bounds (idx<16) (7<idx)
and $v0, $v0, $v1
ori $t5, $0, 7
sltu $v1, $t5, $s2
and $v0, $v0, $v1
mtc0 $0, $10, 0 # Verify the index data
tlbr
mfc0 $s3, $2, 0 # (EntryLo0)
mfc0 $s4, $3, 0 # (EntryLo1)
mfc0 $s5, $5, 0 # (PageMask)
mfc0 $s6, $10, 0 # (EntryHi)
subu $v1, $t2, $s3 # Validate read
sltiu $v1, $v1, 1
and $v0, $v0, $v1
subu $v1, $t2, $s4
sltiu $v1, $v1, 1
and $v0, $v0, $v1
subu $v1, $t3, $s5
sltiu $v1, $v1, 1
and $v0, $v0, $v1
subu $v1, $t4, $s6
sltiu $v1, $v1, 1
and $v0, $v0, $v1
#### Test code end ####
sw $v0, 8($s0) # Set the test result
sw $s1, 4($s0) # Set 'done'
$done:
jr $ra
nop
.end test
mipsevm/test/xop_flush.asm deleted 100644 → 0
View file @ 57a15673
###############################################################################
# File : xop_flush.asm
# Project : MIPS32 MUX
# Author: : Grant Ayers (ayers@cs.stanford.edu)
#
# Standards/Formatting:
# MIPS gas, soft tab, 80 column
#
# Description:
# Test for proper flushing caused by serialized XOP instructions
#
###############################################################################
.section .test, "x"
.balign 4
.set noreorder
.global test
.ent test
test:
lui $s0, 0xbfff # Load the base address 0xbffffff0
ori $s0, 0xfff0
ori $s1, $0, 1 # Prepare the 'done' status
#### Test code start ####
setup:
mfc0 $k0, $12, 0 # Load the Status register
lui $k1, 0x1000 # Allow access to CP0
or $k0, $k0, $k1
lui $k1, 0x1dff # Disable CP3-1, No RE, keep BEV
ori $k1, 0x00e6 # No interrupts, use kernel mode
and $k0, $k0, $k1
mtc0 $k0, $12, 0
la $k0, enable_cache # Set ErrorEPC so we continue after the reset exception
mtc0 $k0, $30, 0
eret
enable_cache:
mfc0 $t0, $16, 0 # Enable kseg0 caching (Config:K0 = 0x3)
lui $t1, 0xffff
ori $t1, 0xfff8
and $t0, $t0, $t1
ori $t0, 0x3
mtc0 $t0, $16, 0
la $t1, $cache_on # Run the rest of the code with the i-cache enabled (kseg0)
lui $t0, 0xdfff
ori $t0, 0xffff
and $t1, $t1, $t0 # Clearing bit 29 of a kseg1 address moves it to kseg0
jr $t1
li $v0, 1 # Initialize the test result (1 is pass)
$cache_on:
jal test_1
nop
jal test_2
nop
j $end
nop
test_1: # Interleave XOP/regular instructions, verify execution counts
li $t0, 0
mtc0 $0, $11, 0 # Use 'Compare' as a scratch register in CP0
addiu $t0, $t0, 1
mtc0 $0, $11, 0
mtc0 $0, $11, 0
addiu $t0, $t0, 1
mtc0 $0, $11, 0
mtc0 $0, $11, 0
mtc0 $0, $11, 0
addiu $t0, $t0, 1
mtc0 $0, $11, 0
mtc0 $0, $11, 0
mtc0 $0, $11, 0
mtc0 $0, $11, 0
addiu $t0, $t0, 1
addiu $t0, $t0, 1
mtc0 $0, $11, 0
addiu $t0, $t0, 1
mtc0 $0, $11, 0
addiu $t0, $t0, 1
addiu $t0, $t0, 1
addiu $t0, $t0, 1
addiu $t0, $t0, 1
addiu $t0, $t0, 1
addiu $t0, $t0, 1
addiu $t0, $t0, 1
addiu $t0, $t0, 1
mtc0 $0, $11, 0
addiu $t0, $t0, 1
addiu $t0, $t0, 1
addiu $t0, $t0, 1
addiu $t0, $t0, 1
mtc0 $0, $11, 0
mtc0 $0, $11, 0
mtc0 $0, $11, 0
addiu $t0, $t0, 1
mtc0 $0, $11, 0
mtc0 $0, $11, 0
mtc0 $0, $11, 0
addiu $t0, $t0, 1
addiu $v1, $t0, -20
sltiu $v1, $v1, 1
and $v0, $v0, $v1
jr $ra
nop
test_2: # Cause an exception in a flush slot. It shouldn't fire
lui $t0, 0x7fff
ori $t0, 0xffff
syscall # The handler will set t0 to 0
addi $t0, 1 # Arithmetic overflow exception
addi $t0, 1
addi $t0, 1
addi $t0, 1
addi $t0, 1
addi $t0, 1
addi $t0, 1
addi $t0, 1
jr $ra
nop
$end:
#### Test code end ####
sw $v0, 8($s0) # Set the test result
sw $s1, 4($s0) # Set 'done'
$done:
jr $ra
nop
.end test
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