we don't have dcache/icache

contracts/MIPSMemory.sol

@@ -20,6 +20,8 @@ contract MIPSMemory {
     // TODO: do the real stateHash mutation
     bytes32 newstateHash = keccak256(abi.encodePacked(stateHash));
 
+    // note that zeros are never stored in the trie, so storing a 0 is a delete
+
     // no proof required, this is obviously right
     //state[newstateHash][addr] = (1 << 32) | value;
 

mipsevm/README

@@ -14,4 +14,12 @@ Tests from https://github.com/grantae/OpenMIPS/tree/master/software/test/macro/t
 Licensed GPLv3
 
 Instruction set used by minigeth, 55 instructions:
-['addi', 'addiu', 'addu', 'and', 'andi', 'b', 'beq', 'beqz', 'bgez', 'bgtz', 'blez', 'bltz', 'bne', 'bnez', 'clz', 'divu', 'j', 'jal', 'jalr', 'jr', 'lb', 'lbu', 'lui', 'lw', 'lwr', 'mfhi', 'mflo', 'move', 'movn', 'movz', 'mtlo', 'mul', 'multu', 'negu', 'nop', 'not', 'or', 'ori', 'sb', 'sll', 'sllv', 'slt', 'slti', 'sltiu', 'sltu', 'sra', 'srl', 'srlv', 'subu', 'sw', 'swr', 'sync', 'syscall', 'xor', 'xori']
+['addi', 'addiu', 'addu', 'and', 'andi',
+ 'b', 'beq', 'beqz', 'bgez', 'bgtz', 'blez', 'bltz', 'bne', 'bnez',
+ 'clz', 'divu',
+ 'j', 'jal', 'jalr', 'jr',
+ 'lb', 'lbu', 'lui', 'lw', 'lwr',
+ 'mfhi', 'mflo', 'move', 'movn', 'movz', 'mtlo', 'mul', 'multu',
+ 'negu', 'nop', 'not', 'or', 'ori',
+ 'sb', 'sll', 'sllv', 'slt', 'slti', 'sltiu', 'sltu', 'sra', 'srl', 'srlv', 'subu', 'sw', 'swr', 'sync', 'syscall',
+ 'xor', 'xori']

mipsevm/test/dcache_adrhinv.asm

-###############################################################################
-# File         : dcache_adrhinv.asm
-# Project      : MIPS32 MUX
-# Author:      : Grant Ayers (ayers@cs.stanford.edu)
-#
-# Standards/Formatting:
-#   MIPS gas, soft tab, 80 column
-#
-# Description:
-#   Test the address hit invalidate operation on the dcache
-#
-###############################################################################
-
-
-    .section .test, "x"
-    .balign 4
-    .set    noreorder
-    .global test
-    .ent    test
-test:
-    lui     $s0, 0xbfff         # Load the base address 0xbffffff0
-    ori     $s0, 0xfff0
-    ori     $s1, $0, 1          # Prepare the 'done' status
-
-    #### Test code start ####
-
-    mfc0    $t0, $16, 0         # Enable kseg0 caching (Config:K0 = 0x3)
-    lui     $t1, 0xffff
-    ori     $t1, 0xfff8
-    and     $t0, $t0, $t1
-    ori     $t0, 0x3
-    mtc0    $t0, $16, 0
-    la      $t1, $cache_on      # Run this code with the i-cache enabled by jumping to the cacheable address
-    lui     $t0, 0xdfff
-    ori     $t0, 0xffff
-    and     $t1, $t1, $t0
-    jr      $t1
-    li      $v0, 1              # Initialize the test result (1 is pass)
-$cache_on:
-    la      $s2, word           # Uncacheable address for 'word' in kseg1
-    la      $s3, word           # Cacheable address of 'word' in kseg0 (set below)
-    lui     $t0, 0xdfff
-    ori     $t0, 0xffff
-    and     $s3, $s3, $t0       # Clearing bit 29 changes a kseg1 address to kseg0
-    jal     test1
-    nop
-    jal     test2
-    nop
-    jal     test3
-    nop
-    j       $end
-    nop
-
-test1: # No Writeback: Load to cache, modify, invalidate => memory/uncached value should not be updated
-    lw      $t1, 0($s3)         # Load 'word' into the cache
-    addiu   $v1, $t1, -1234     # Sanity check that the load worked
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    li      $t0, 4321           # Modify 'word' in the cache
-    sw      $t0, 0($s3)
-    lw      $t0, 0($s3)         # Sanity check that the store worked
-    addiu   $v1, $t0, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    cache   0x11, 0($s3)        # Invalidate 'word' in the cache (11 <=> {3'AdrHitInv, 2'L1-DCache})
-    lw      $t2, 0($s2)         # Check that the (uncached) memory word was not updated
-    addiu   $v1, $t2, -1234
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    jr      $ra
-    nop
-
-test2: # Invalidate: Load to cache, invalidate, write uncached, load to cache => new value in cache
-    lw      $t1, 0($s3)         # Load 'word' into the cache
-    addiu   $v1, $t1, -1234     # Sanity check that the load worked
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    cache   0x15, 0($s3)        # Remove 'word' from the cache
-    li      $t0, 4321           # Modify 'word' in memory
-    sw      $t0, 0($s2)
-    lw      $t1, 0($s3)         # Load 'word' to the cache. It should have the new value
-    addiu   $v1, $t1, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    li      $t0, 1234           # Restore 'word' for the next test
-    sw      $t0, 0($s2)
-    jr      $ra
-    sw      $t0, 0($s3)
-
-test3: # Invalidate: Load to cache, modify, write uncached, invalidate, load to cache => new value in cache
-    lw      $t1, 0($s3)         # Load 'word' into the cache
-    addiu   $v1, $t1, -1234     # Sanity check that the load worked
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    li      $t0, 777            # Modify 'word' in the cache
-    sw      $t0, 0($s3)
-    li      $t0, 4321           # Modify 'word' in memory
-    sw      $t0, 0($s2)
-    cache   0x11, 0($s3)        # Remove 'word' from the cache
-    lw      $t1, 0($s3)         # Load 'word' to the cache. It should have the new uncached value
-    addiu   $v1, $t1, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    jr      $ra
-    nop
-
-$end:
-    #### Test code end ####
-
-    sw      $v0, 8($s0)         # Set the test result
-    sw      $s1, 4($s0)         # Set 'done'
-
-$done:
-    jr      $ra
-    nop
-
-    .balign 4096                # Place this code at address 0xXXXXX{3,7,b,f}30, which is the arbitrary
-    .skip 0xaa0, 0              #   index 0x33 (51) for a 2 KiB 2-way 16-byte-block cache
-word:
-    .word 0x000004d2            # Arbitrary value (1234) indicating the data is unchanged
-
-    .end test

mipsevm/test/dcache_adrhwbinv.asm

-###############################################################################
-# File         : dcache_adrhwbinv.asm
-# Project      : MIPS32 MUX
-# Author:      : Grant Ayers (ayers@cs.stanford.edu)
-#
-# Standards/Formatting:
-#   MIPS gas, soft tab, 80 column
-#
-# Description:
-#   Test the address hit writeback invalidate operation on the dcache
-#
-###############################################################################
-
-
-    .section .test, "x"
-    .balign 4
-    .set    noreorder
-    .global test
-    .ent    test
-test:
-    lui     $s0, 0xbfff         # Load the base address 0xbffffff0
-    ori     $s0, 0xfff0
-    ori     $s1, $0, 1          # Prepare the 'done' status
-
-    #### Test code start ####
-
-    mfc0    $t0, $16, 0         # Enable kseg0 caching (Config:K0 = 0x3)
-    lui     $t1, 0xffff
-    ori     $t1, 0xfff8
-    and     $t0, $t0, $t1
-    ori     $t0, 0x3
-    mtc0    $t0, $16, 0
-    la      $t1, $cache_on      # Run this code with the i-cache enabled by jumping to the cacheable address
-    lui     $t0, 0xdfff
-    ori     $t0, 0xffff
-    and     $t1, $t1, $t0
-    jr      $t1
-    nop
-$cache_on:
-    la      $s2, word           # Uncacheable address for 'word' in kseg1
-    la      $s3, word           # Cacheable address of 'word' in kseg0 (set below)
-    lui     $t0, 0xdfff
-    ori     $t0, 0xffff
-    and     $s3, $s3, $t0       # Clearing bit 29 changes a kseg1 address to kseg0
-    jal     test1
-    nop
-    jal     test2
-    nop
-    jal     test3
-    nop
-    j       $end
-    nop
-
-test1: # Writeback: Load to cache, modify, invalidate => memory/uncached value should be updated
-    lw      $t1, 0($s3)         # Load 'word' into the cache
-    addiu   $v1, $t1, -1234     # Sanity check that the load worked
-    sltiu   $v0, $v1, 1
-    li      $t0, 4321           # Modify 'word' in the cache
-    sw      $t0, 0($s3)
-    lw      $t0, 0($s3)         # Sanity check that the store worked
-    addiu   $v1, $t0, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    cache   0x15, 0($s3)        # Invalidate 'word' writing it back to memory (15 <=> {3'AdrHitWbInv, 2'L1-DCache})
-    lw      $t2, 0($s2)         # Check that the (uncached) memory word was updated
-    addiu   $v1, $t2, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    li      $t0, 1234           # Restore 'word' for the next test
-    jr      $ra
-    sw      $t0, 0($s2)
-
-test2: # Invalidate: Load to cache, invalidate, write uncached, load to cache => new value in cache
-    lw      $t1, 0($s3)         # Load 'word' into the cache
-    addiu   $v1, $t1, -1234     # Sanity check that the load worked
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    cache   0x15, 0($s3)        # Remove 'word' from the cache
-    li      $t0, 4321           # Modify 'word' in memory
-    sw      $t0, 0($s2)
-    lw      $t1, 0($s3)         # Load 'word' to the cache. It should have the new value
-    addiu   $v1, $t1, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    li      $t0, 1234           # Restore 'word' for the next test
-    sw      $t0, 0($s2)
-    jr      $ra
-    sw      $t0, 0($s3)
-
-test3: # Invalidate: Load to cache, modify, invalidate, write uncached, load to cache => new value in cache
-    lw      $t1, 0($s3)         # Load 'word' into the cache
-    addiu   $v1, $t1, -1234     # Sanity check that the load worked
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    li      $t0, 777            # Modify 'word' in the cache
-    sw      $t0, 0($s3)
-    cache   0x15, 0($s3)        # Remove 'word' from the cache
-    li      $t0, 4321           # Modify 'word' in memory
-    sw      $t0, 0($s2)
-    lw      $t1, 0($s3)         # Load 'word' to the cache. It should have the new value
-    addiu   $v1, $t1, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    jr      $ra
-    nop
-
-$end:
-    #### Test code end ####
-
-    sw      $v0, 8($s0)         # Set the test result
-    sw      $s1, 4($s0)         # Set 'done'
-
-$done:
-    jr      $ra
-    nop
-
-    .balign 4096                # Place this code at address 0xXXXXX{3,7,b,f}30, which is the arbitrary
-    .skip 0xaa0, 0              #   index 0x33 (51) for a 2 KiB 2-way 16-byte-block cache
-word:
-    .word 0x000004d2            # Arbitrary value (1234) indicating the data is unchanged
-
-    .end test

mipsevm/test/dcache_idxwbinv.asm

-###############################################################################
-# File         : dcache_idxwbinv.asm
-# Project      : MIPS32 MUX
-# Author:      : Grant Ayers (ayers@cs.stanford.edu)
-#
-# Standards/Formatting:
-#   MIPS gas, soft tab, 80 column
-#
-# Description:
-#   Test the index writeback invalidate operation on the dcache
-#
-###############################################################################
-
-
-    .section .test, "x"
-    .balign 4
-    .set    noreorder
-    .global test
-    .ent    test
-test:
-    lui     $s0, 0xbfff         # Load the base address 0xbffffff0
-    ori     $s0, 0xfff0
-    ori     $s1, $0, 1          # Prepare the 'done' status
-
-    #### Test code start ####
-
-    mfc0    $t0, $16, 0         # Enable kseg0 caching (Config:K0 = 0x3)
-    lui     $t1, 0xffff
-    ori     $t1, 0xfff8
-    and     $t0, $t0, $t1
-    ori     $t0, 0x3
-    mtc0    $t0, $16, 0
-    la      $s2, word           # Uncacheable address for 'word' in kseg1
-    la      $s3, word           # Cacheable address of 'word' in kseg0
-    lui     $t0, 0xdfff         #  (clear bit 29 to change from kseg1 to kseg0)
-    ori     $t0, 0xffff
-    and     $s3, $s3, $t0
-    lw      $t1, 0($s3)         # Load 'word' into the cache
-    addiu   $v1, $t1, -1234     # Sanity check that the load worked
-    sltiu   $v0, $v1, 1
-    li      $t0, 4321           # Store a new value to 'word' in the cache
-    sw      $t0, 0($s3)
-    lw      $t2, 0($s3)         # Sanity check that the store worked (new value)
-    addiu   $v1, $t2, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    lw      $t3, 0($s2)         # Verify that the uncached value did not update
-    addiu   $v1, $t3, -1234
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    lui     $t0, 0x8000         # Invalidate index 0x33 (51) for both ways (1 KiB apart)
-    cache   0x1, 0x0330($t0)    # 0x1 <=> {000, 01} <=> {IdxWbInv, L1-DCache}
-    cache   0x1, 0x0730($t0)
-    lw      $t4, 0($s2)         # Load 'word1' uncached (should have new value)
-    addiu   $v1, $t4, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v1, $v1
-    j       $end                # Set the result and finish
-    nop
-
-    .balign 1024                # Place this code at address 0xXXXXX{3,7,b,f}30, which is the arbitrary
-    .skip 0x330, 0              #   index 0x33 (51) for a 2 KiB 2-way 16-byte-block cache
-word:
-    .word 0x000004d2            # Arbitrary value (1234) indicating the data is unchanged
-
-$end:
-    #### Test code end ####
-
-    sw      $v0, 8($s0)         # Set the test result
-    sw      $s1, 4($s0)         # Set 'done'
-
-$done:
-    jr      $ra
-    nop
-
-    .end test

mipsevm/test/dcache_stag1.asm

-###############################################################################
-# File         : dcache_stag1.asm
-# Project      : MIPS32 MUX
-# Author:      : Grant Ayers (ayers@cs.stanford.edu)
-#
-# Standards/Formatting:
-#   MIPS gas, soft tab, 80 column
-#
-# Description:
-#   Test the index store tag operation on the dcache: Invalidate a block
-#
-###############################################################################
-
-
-    .section .test, "x"
-    .balign 4
-    .set    noreorder
-    .global test
-    .ent    test
-test:
-    lui     $s0, 0xbfff         # Load the base address 0xbffffff0
-    ori     $s0, 0xfff0
-    ori     $s1, $0, 1          # Prepare the 'done' status
-
-    #### Test code start ####
-
-    mfc0    $t0, $16, 0         # Enable kseg0 caching (Config:K0 = 0x3)
-    lui     $t1, 0xffff
-    ori     $t1, 0xfff8
-    and     $t0, $t0, $t1
-    ori     $t0, 0x3
-    mtc0    $t0, $16, 0
-    la      $t1, $cache_on      # Run the rest of the code with the i-cache enabled (kseg0)
-    lui     $t0, 0xdfff
-    ori     $t0, 0xffff
-    and     $t1, $t1, $t0       # Clearing bit 29 of a kseg1 address moves it to kseg0
-    j       $t1
-    nop
-$cache_on:
-    la      $s2, word           # Uncacheable address for 'word' in kseg1
-    la      $s3, word           # Cacheable address of 'word' in kseg0
-    and     $s3, $s3, $t0       # Clearing bit 29 of a kseg1 address moves it to kseg0
-    lw      $t1, 0($s3)         # Load 'word' into the cache
-    addiu   $v1, $t1, -1234     # Sanity check that the load worked
-    sltiu   $v0, $v1, 1
-    li      $t2, 4321           # Store a new value to 'word' in the cache
-    sw      $t2, 0($s3)
-    lw      $t1, 0($s3)         # Sanity check that the store worked (new value)
-    addiu   $v1, $t1, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    mtc0    $0, $28, 0          # Prepare TagHi/TagLo for invalidation
-    mtc0    $0, $29, 0
-    lui     $t0, 0x8000         # Invalidate index 0x33 (51) for both ways (1 KiB apart)
-    cache   0x9, 0x0330($t0)    # 0x9 <=> {010, 01} <=> {IdxStoreTag, L1-DCache}
-    cache   0x9, 0x0730($t0)
-    lw      $t3, 0($s2)         # Load 'word' from memory. It should be the old value
-    addiu   $v1, $t3, -1234
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    lw      $t4, 0($s3)         # Load again but cached. Expect the old value still
-    addiu   $v1, $t4, -1234
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    j       $end                # Set the result and finish
-    nop
-
-    .balign 1024                # Place this code at address 0xXXXXX{3,7,b,f}30, which is the arbitrary
-    .skip 0x330, 0              #   index 0x33 (51) for a 2 KiB 2-way 16-byte-block cache
-word:
-    .word 0x000004d2            # Arbitrary value (1234) indicating the data is unchanged
-
-$end:
-    #### Test code end ####
-
-    sw      $v0, 8($s0)         # Set the test result
-    sw      $s1, 4($s0)         # Set 'done'
-
-$done:
-    jr      $ra
-    nop
-
-    .end test

mipsevm/test/dcache_stag2.asm

-###############################################################################
-# File         : dcache_stag2.asm
-# Project      : MIPS32 MUX
-# Author:      : Grant Ayers (ayers@cs.stanford.edu)
-#
-# Standards/Formatting:
-#   MIPS gas, soft tab, 80 column
-#
-# Description:
-#   Test index store tag operation on the dcache: Change a tag to a new address
-#
-###############################################################################
-
-
-    .section .test, "x"
-    .balign 4
-    .set    noreorder
-    .global test
-    .ent    test
-test:
-    lui     $s0, 0xbfff         # Load the base address 0xbffffff0
-    ori     $s0, 0xfff0
-    ori     $s1, $0, 1          # Prepare the 'done' status
-
-    #### Test code start ####
-
-    mfc0    $t0, $16, 0         # Enable kseg0 caching (Config:K0 = 0x3)
-    lui     $t1, 0xffff
-    ori     $t1, 0xfff8
-    and     $t0, $t0, $t1
-    ori     $t0, 0x3
-    mtc0    $t0, $16, 0
-    la      $s2, word1          # Uncacheable address of 'word1' in kseg1
-    la      $s3, word1          # Cacheable address of 'word1' in kseg1 (set below)
-    la      $s4, word2          # Uncacheable address of 'word2' in kseg1
-    la      $s5, word2          # Cacheable address of 'word2' in kseg0 (set below)
-    lui     $t0, 0xdfff
-    ori     $t0, 0xffff
-    and     $s3, $s3, $t0       # Clearing bit 29 changes a kseg1 address to kseg0
-    and     $s5, $s5, $t0
-    lw      $t1, 0($s3)         # Load 'word1' into the cache
-    addiu   $v1, $t1, -1234     # Sanity check that the load worked
-    sltiu   $v0, $v1, 1
-    li      $t0, 7777
-    sw      $t0, 0($s3)         # Change the value of 'word1' in the cache
-    lw      $t2, 0($s3)         # Sanity check that the store worked
-    addiu   $v1, $t2, -7777
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    lui     $t0, 0x1fff         # Compute the physical address of 'word2'
-    ori     $t0, 0xffff
-    and     $t3, $t0, $s4
-    srl     $t3, $t3, 1         # TagLo format is {1'b0, 23'b(Tag), 2'b(State), 6'b0}
-    lui     $t0, 0xffff
-    ori     $t0, 0xff00
-    and     $t3, $t3, $t0
-    ori     $t3, 0x00c0         # If any bit of State (TagLo[7:6]) is high => valid (if both => dirty)
-    mtc0    $t3, $28, 0         # Send the tag to TagLo and zero TagHi
-    mtc0    $0,  $29, 0
-    lui     $t0, 0x8000         # Change the tag of 'word1' to 'word2' (assumes data is in set A!)
-    cache   0x9, 0x0730($t0)    # 0x9 <=> {010, 01} <=> {IdxStoreTag, L1-DCache}
-    lw      $t4, 0($s5)         # Load 'word2' from the cache. It should contain '7777'
-    addiu   $v1, $t4, -7777
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    lw      $t5, 0($s4)         # Load 'word2' uncached. It should be the original value
-    addiu   $v1, $t5, -4321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    lw      $t6, 0($s3)         # Load 'word1' cached. It should be the original value
-    addiu   $v1, $t6, -1234
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    j       $end                # Set the result and finish
-    nop
-
-    .balign 1024                # Place this code at address 0xXXXXX{3,7,b,f}30, which is the arbitrary
-    .skip 0x330, 0              #   index 0x33 (51) for a 2 KiB 2-way 16-byte-block cache
-word1:
-    .word 0x000004d2            # Arbitrary value (1234) indicating the data is unchanged
-
-    .balign 1024                # Move to another address with the same set index
-    .skip 0x330, 0
-word2:
-    .word 0x000010e1            # Arbitrary value (4321)
-
-$end:
-    #### Test code end ####
-
-    sw      $v0, 8($s0)         # Set the test result
-    sw      $s1, 4($s0)         # Set 'done'
-
-$done:
-    jr      $ra
-    nop
-
-    .end test

mipsevm/test/icache_adrhinv.asm

-###############################################################################
-# File         : icache_adrhinv.asm
-# Project      : MIPS32 MUX
-# Author:      : Grant Ayers (ayers@cs.stanford.edu)
-#
-# Standards/Formatting:
-#   MIPS gas, soft tab, 80 column
-#
-# Description:
-#   Test the address hit invalidate operation on the icache
-#
-###############################################################################
-
-
-    .section .test, "x"
-    .balign 4
-    .set    noreorder
-    .global test
-    .ent    test
-test:
-    lui     $s0, 0xbfff         # Load the base address 0xbffffff0
-    ori     $s0, 0xfff0
-    ori     $s1, $0, 1          # Prepare the 'done' status
-
-    #### Test code start ####
-
-    mfc0    $t0, $16, 0         # Enable kseg0 caching (Config:K0 = 0x3)
-    lui     $t1, 0xffff
-    ori     $t1, 0xfff8
-    and     $t0, $t0, $t1
-    ori     $t0, 0x3
-    mtc0    $t0, $16, 0
-    la      $t0, $cache_on      # Run the remainder of the code from the i-cache
-    lui     $t1, 0xdfff
-    ori     $t1, 0xffff
-    and     $t0, $t0, $t1
-    jr      $t0
-    nop
-$cache_on:
-    la      $s2, $mutable       # Run the mutable code once in kseg0 to cache it
-    lui     $t0, 0xdfff         #   (Clear bit 29 to change the address from kseg1 to kseg0)
-    ori     $t0, 0xffff
-    and     $s2, $s2, $t0
-    jalr    $s2
-    nop
-    addiu   $v1, $s7, -123      # Sanity check the call result
-    sltiu   $v0, $v1, 1
-    la      $t0, $mutable       # Replace the mutable instruction with "li $s7, 321"
-    lui     $s3, 0x2417
-    ori     $s3, 0x0141
-    sw      $s3, 0($t0)         # This address is in kseg1, hence uncacheable so it will go to mem
-    jalr    $s2                 # Call the cacheable version again to verify it was actually
-    nop                         #   cached--if so it will give the old value
-    addiu   $v1, $s7, -123
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    cache   0x10, 0($t0)        # Test 1: Invalidate via the kseg1 address
-                                # 0x10 <=> {100, 00} <=> {AddrHitInvalidate, L1-ICache}
-    jalr    $s2                 # Call the cacheable version. If the invalidation worked it will
-    nop                         #   pull the new instruction from memory which sets '321'. Otherwise
-                                #   the invalidation (or uncacheable store) failed.
-    addiu   $v1, $s7, -321
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    lui     $s4, 0x2417         # Replace the new instruction with the original version
-    ori     $s4, 0x007b
-    sw      $s4, 0($t0)
-    cache   0x10, 0($t0)        # Test 2: Invalidate via the kseg0 address
-    jalr    $s2                 # Cacheable version again. Should give '123'
-    nop
-    addiu   $v1, $s7, -123
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-
-$end:
-    #### Test code end ####
-
-    sw      $v0, 8($s0)         # Set the test result
-    sw      $s1, 4($s0)         # Set 'done'
-
-$done:
-    jr      $ra
-    nop
-
-    .balign 4096                # Place this code at address 0xXXXXXaa0, which is the arbitrary
-    .skip 0xaa0, 0              #   index 0xaa (170) for an 8 KiB 2-way 16-byte block cache
-$mutable:
-    li      $s7, 123            # The arbitrary number 123 indicates the instruction is unchanged
-    jr      $ra
-    nop
-
-    .end test

mipsevm/test/icache_idxinv.asm

-###############################################################################
-# File         : icache_idxinv.asm
-# Project      : MIPS32 MUX
-# Author:      : Grant Ayers (ayers@cs.stanford.edu)
-#
-# Standards/Formatting:
-#   MIPS gas, soft tab, 80 column
-#
-# Description:
-#   Test the index invalidate tag operation on the icache
-#
-###############################################################################
-
-
-    .section .test, "x"
-    .balign 4
-    .set    noreorder
-    .global test
-    .ent    test
-test:
-    lui     $s0, 0xbfff         # Load the base address 0xbffffff0
-    ori     $s0, 0xfff0
-    ori     $s1, $0, 1          # Prepare the 'done' status
-
-    #### Test code start ####
-
-    mfc0    $t0, $16, 0         # Enable kseg0 caching (Config:K0 = 0x3)
-    lui     $t1, 0xffff
-    ori     $t1, 0xfff8
-    and     $t0, $t0, $t1
-    ori     $t0, 0x3
-    mtc0    $t0, $16, 0
-    la      $t0, $cache_on      # Run the remainder of the code from the i-cache
-    lui     $t1, 0xdfff
-    ori     $t1, 0xffff
-    and     $t0, $t0, $t1
-    jr      $t0
-    nop
-$cache_on:
-    la      $s2, $mutable       # Run the mutable code once in kseg0 to cache it
-    lui     $t0, 0xdfff         #   (Clear bit 29 to change the address from kseg1 to kseg0)
-    ori     $t0, 0xffff
-    and     $s2, $s2, $t0
-    jalr    $s2
-    nop
-    addiu   $v1, $s7, -123      # Sanity check the call result
-    sltiu   $v0, $v1, 1
-    la      $t0, $mutable       # Replace the mutable instruction with "li $s7, 321"
-    lui     $t1, 0x2417
-    ori     $t1, 0x0141
-    sw      $t1, 0($t0)         # This address is in kseg1, hence uncacheable so it will go to mem
-    jalr    $s2                 # Call the cacheable version again to verify it was actually
-    nop                         #   cached--if so it will give the old value
-    addiu   $v1, $s7, -123
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    lui     $s3, 0x8000         # Invalidate the cache index 0xaa (170) for both sets (4 KiB apart)
-    cache   0x0, 0x0aa0($s3)    # 0x8 <=> {010, 00} <=> {IndexStoreTag, L1-ICache}
-    cache   0x0, 0x1aa0($s3)
-    jalr    $s2                 # Call the cacheable version. If the invalidation worked it will
-    nop                         #   pull the new instruction from memory which sets '321'. Otherwise
-    addiu   $v1, $s7, -321      #   the invalidation (or uncacheable store) failed.
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-
-$end:
-    #### Test code end ####
-
-    sw      $v0, 8($s0)         # Set the test result
-    sw      $s1, 4($s0)         # Set 'done'
-
-$done:
-    jr      $ra
-    nop
-
-    .balign 4096                # Place this code at address 0xXXXXXaa0, which is the arbitrary
-    .skip 0xaa0, 0              #   index 0xaa (170) for an 8 KiB 2-way 16-byte block cache
-$mutable:
-    li      $s7, 123            # The arbitrary number 123 indicates the instruction is unchanged
-    jr      $ra
-    nop
-
-    .end test

mipsevm/test/icache_stag1.asm

-###############################################################################
-# File         : icache_stag1.asm
-# Project      : MIPS32 MUX
-# Author:      : Grant Ayers (ayers@cs.stanford.edu)
-#
-# Standards/Formatting:
-#   MIPS gas, soft tab, 80 column
-#
-# Description:
-#   Test the index store tag operation on the icache: Invalidate a block
-#
-###############################################################################
-
-
-    .section .test, "x"
-    .balign 4
-    .set    noreorder
-    .global test
-    .ent    test
-test:
-    lui     $s0, 0xbfff         # Load the base address 0xbffffff0
-    ori     $s0, 0xfff0
-    ori     $s1, $0, 1          # Prepare the 'done' status
-
-    #### Test code start ####
-
-    mtc0    $0,  $28, 0         # Prepare the TagLo/TagHi invalidation value
-    mtc0    $0,  $29, 0
-    mfc0    $t0, $16, 0         # Enable kseg0 caching (Config:K0 = 0x3)
-    lui     $t1, 0xffff
-    ori     $t1, 0xfff8
-    and     $t0, $t0, $t1
-    ori     $t0, 0x3
-    mtc0    $t0, $16, 0
-    la      $t0, $cache_on      # Run the remainder of the code from the i-cache
-    lui     $t1, 0xdfff
-    ori     $t1, 0xffff
-    and     $t0, $t0, $t1
-    jr      $t0
-    nop
-$cache_on:
-    la      $s2, $mutable       # Run the mutable code once in kseg0 to cache it
-    lui     $t0, 0xdfff         #   (Clear bit 29 to change the address from kseg1 to kseg0)
-    ori     $t0, 0xffff
-    and     $s2, $s2, $t0
-    jalr    $s2
-    nop
-    addiu   $v1, $s7, -123      # Sanity check the call result
-    sltiu   $v0, $v1, 1
-    la      $t0, $mutable       # Replace the mutable instruction with "li $s7, 321"
-    lui     $t1, 0x2417
-    ori     $t1, 0x0141
-    sw      $t1, 0($t0)         # This address is in kseg1, hence uncacheable so it will go to mem
-    jalr    $s2                 # Call the cacheable version again to verify it was actually
-    nop                         #   cached--if so it will give the old value
-    addiu   $v1, $s7, -123
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-    lui     $s3, 0x8000         # Invalidate the cache index 0xaa (170) for both sets (4 KiB apart)
-    cache   0x8, 0x0aa0($s3)    # 0x8 <=> {010, 00} <=> {IndexStoreTag, L1-ICache}
-    cache   0x8, 0x1aa0($s3)
-    jalr    $s2                 # Call the cacheable version. If the invalidation worked it will
-    nop                         #   pull the new instruction from memory which sets '321'. Otherwise
-    addiu   $v1, $s7, -321      #   the invalidation (or uncacheable store) failed.
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-
-$end:
-    #### Test code end ####
-
-    sw      $v0, 8($s0)         # Set the test result
-    sw      $s1, 4($s0)         # Set 'done'
-
-$done:
-    jr      $ra
-    nop
-
-    .balign 4096                # Place this code at address 0xXXXXXaa0, which is the arbitrary
-    .skip 0xaa0, 0              #   index 0xaa (170) for an 8 KiB 2-way 16-byte block cache
-$mutable:
-    li      $s7, 123            # The arbitrary number 123 indicates the instruction is unchanged
-    jr      $ra
-    nop
-
-    .end test

mipsevm/test/icache_stag2.asm

-###############################################################################
-# File         : icache_stag2.asm
-# Project      : MIPS32 MUX
-# Author:      : Grant Ayers (ayers@cs.stanford.edu)
-#
-# Standards/Formatting:
-#   MIPS gas, soft tab, 80 column
-#
-# Description:
-#   Test index store tag operation on the icache: Change a tag to a new address
-#
-###############################################################################
-
-
-    .section .test, "x"
-    .balign 4
-    .set    noreorder
-    .global test
-    .ent    test
-test:
-    lui     $s0, 0xbfff         # Load the base address 0xbffffff0
-    ori     $s0, 0xfff0
-    ori     $s1, $0, 1          # Prepare the 'done' status
-
-    #### Test code start ####
-
-    # Procedure: Load procA to cache, change tag to procB, jump to procB and it should execute procA.
-
-    mfc0    $t0, $16, 0         # Enable kseg0 caching (Config:K0 = 0x3)
-    lui     $t1, 0xffff
-    ori     $t1, 0xfff8
-    and     $t0, $t0, $t1
-    ori     $t0, 0x3
-    mtc0    $t0, $16, 0
-    la      $t0, $cache_on      # Run the remainder of the code from the i-cache
-    lui     $t8, 0xdfff
-    ori     $t8, 0xffff
-    and     $t0, $t0, $t8
-    jr      $t0
-    nop
-$cache_on:
-    la      $s2, $procedureA    # Run procedure A once in kseg0 to cache it
-    lui     $t0, 0xdfff         #   (Clear bit 29 to change the address from kseg1 to kseg0)
-    ori     $t0, 0xffff
-    and     $s2, $s2, $t0
-    jalr    $s2
-    nop
-    addiu   $v1, $s7, -123      # Sanity check the call result
-    sltiu   $v0, $v1, 1
-    la      $s3, $procedureB    # Compute the physical tag of procedureB
-    lui     $t0, 0xdfff
-    ori     $t0, 0xffff
-    and     $s3, $s3, $t0       # kseg0 address of procedureB
-    lui     $t0, 0x1fff
-    ori     $t0, 0xffff
-    and     $t1, $t0, $s3       # Physical address of procedureB
-    srl     $t2, $t1, 1         # TagLo format is {1'b0, 23'b(Tag), 2'b(State), 6'b0}
-    lui     $t0, 0xffff
-    ori     $t0, 0xff00
-    and     $t2, $t2, $t0
-    ori     $t2, 0x00c0         # If any bit of State (TagLo[7:6]) is high => valid
-    mtc0    $t2, $28, 0         # Send the tag to TagLo and zero TagHi
-    mtc0    $0,  $29, 0
-    lui     $t1, 0x8000         # Change the tag for procedureA to procedureB
-    cache   0x8, 0x1aa0($t1)    # 0x8 <=> {010, 00} <=> {IndexStoreTag, L1-ICache}
-                                # NOTE: Assumes the data is in set A! This could break.
-    nop                         # Inject NOPs to prevent the next jump target from entering
-    nop                         #   the pipeline and being 'prefetched' into the cache
-    nop                         #   before the 'cache' operation retires
-    jalr    $s3                 # Call procedureB, which should actually be procedureA
-    nop
-    addiu   $v1, $s7, -123
-    sltiu   $v1, $v1, 1
-    and     $v0, $v0, $v1
-
-$end:
-    #### Test code end ####
-
-    sw      $v0, 8($s0)         # Set the test result
-    sw      $s1, 4($s0)         # Set 'done'
-
-$done:
-    jr      $ra
-    nop
-
-    .balign 4096                # Place this code at address 0xXXXXXaa0, which is the arbitrary
-    .skip 0xaa0, 0              #   index 0xaa (170) for an 8 KiB 2-way 16-byte block cache
-$procedureA:
-    li      $s7, 123            # The arbitrary number 123 indicates the instruction is unchanged
-    jr      $ra
-    nop
-
-    .balign 4096
-    .skip 0xaa0, 0
-$procedureB:
-    li      $s7, 321
-    jr      $ra
-    nop
-
-    .end test

mipsevm/test/icache_tlbl.asm

-###############################################################################
-# File         : icache_tlbl.asm
-# Project      : MIPS32 MUX
-# Author:      : Grant Ayers (ayers@cs.stanford.edu)
-#
-# Standards/Formatting:
-#   MIPS gas, soft tab, 80 column
-#
-# Description:
-#   Test that an icache operation causes a TLB exception when needed
-#
-###############################################################################
-
-
-    .section .test, "x"
-    .balign 4
-    .set    noreorder
-    .global test
-    .ent    test
-test:
-    lui     $s0, 0xbfff         # Load the base address 0xbffffff0
-    ori     $s0, 0xfff0
-    ori     $s1, $0, 1          # Prepare the 'done' status
-
-    #### Test code start ####
-
-    jal     $setup
-    nop
-    xor     $v0, $v0, $v0
-    la      $ra, $end
-cache_inst:
-    j       $end
-    cache   0x10, 0($0)         # Cause a TLB miss for L1-ICache HitInv
-    nop
-
-$setup:
-    mfc0    $k0, $12, 0         # Load the Status register for general setup
-    lui     $k1, 0x1000         # Allow access to CP0
-    or      $k0, $k0, $k1
-    lui     $k1, 0x1dff         # Disable CP3-1, No RE, BEV
-    ori     $k1, 0x00e6         # Disable all interrupts, kernel mode
-    and     $k0, $k0, $k1
-    mtc0    $k0, $12, 0         # Commit new Status register
-    mtc0    $ra, $30, 0         # Set ErrorEPC to the return address of this call
-    la      $a0, cache_inst     # Used by exception handler for verification
-    eret                        # Exit boot mode and return
-
-$end:
-    #### Test code end ####
-
-    sw      $v0, 8($s0)         # Set the test result
-    sw      $s1, 4($s0)         # Set 'done'
-
-$done:
-    jr      $ra
-    nop
-
-    .end test