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Commit d29775ec authored by refcell.eth's avatar refcell.eth Committed by GitHub
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Inline-comment documentation for MIPS.sol and styling. (#6276)

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op-bindings/bindings/mips.go
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...@@ -31,7 +31,7 @@ var ( ...@@ -31,7 +31,7 @@ var (
// MIPSMetaData contains all meta data concerning the MIPS contract. // MIPSMetaData contains all meta data concerning the MIPS contract.
var MIPSMetaData = &bind.MetaData{ var MIPSMetaData = &bind.MetaData{
ABI: "[{\"inputs\":[],\"name\":\"BRK_START\",\"outputs\":[{\"internalType\":\"uint32\",\"name\":\"\",\"type\":\"uint32\"}],\"stateMutability\":\"view\",\"type\":\"function\"},{\"inputs\":[],\"name\":\"oracle\",\"outputs\":[{\"internalType\":\"contractIPreimageOracle\",\"name\":\"\",\"type\":\"address\"}],\"stateMutability\":\"view\",\"type\":\"function\"},{\"inputs\":[{\"internalType\":\"bytes\",\"name\":\"stateData\",\"type\":\"bytes\"},{\"internalType\":\"bytes\",\"name\":\"proof\",\"type\":\"bytes\"}],\"name\":\"step\",\"outputs\":[{\"internalType\":\"bytes32\",\"name\":\"\",\"type\":\"bytes32\"}],\"stateMutability\":\"nonpayable\",\"type\":\"function\"}]", ABI: "[{\"inputs\":[],\"name\":\"BRK_START\",\"outputs\":[{\"internalType\":\"uint32\",\"name\":\"\",\"type\":\"uint32\"}],\"stateMutability\":\"view\",\"type\":\"function\"},{\"inputs\":[],\"name\":\"oracle\",\"outputs\":[{\"internalType\":\"contractIPreimageOracle\",\"name\":\"\",\"type\":\"address\"}],\"stateMutability\":\"view\",\"type\":\"function\"},{\"inputs\":[{\"internalType\":\"bytes\",\"name\":\"stateData\",\"type\":\"bytes\"},{\"internalType\":\"bytes\",\"name\":\"proof\",\"type\":\"bytes\"}],\"name\":\"step\",\"outputs\":[{\"internalType\":\"bytes32\",\"name\":\"\",\"type\":\"bytes32\"}],\"stateMutability\":\"nonpayable\",\"type\":\"function\"}]",
Bin: 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} }
// MIPSABI is the input ABI used to generate the binding from. // MIPSABI is the input ABI used to generate the binding from.
......
op-bindings/bindings/mips_more.go
View file @ d29775ec
...@@ -13,9 +13,9 @@ const MIPSStorageLayoutJSON = "{\"storage\":[{\"astId\":1000,\"contract\":\"cont ...@@ -13,9 +13,9 @@ const MIPSStorageLayoutJSON = "{\"storage\":[{\"astId\":1000,\"contract\":\"cont
var MIPSStorageLayout = new(solc.StorageLayout) var MIPSStorageLayout = new(solc.StorageLayout)
var MIPSDeployedBin = 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func init() { func init() {
if err := json.Unmarshal([]byte(MIPSStorageLayoutJSON), MIPSStorageLayout); err != nil { if err := json.Unmarshal([]byte(MIPSStorageLayoutJSON), MIPSStorageLayout); err != nil {
......
packages/contracts-bedrock/contracts/cannon/MIPS.sol
View file @ d29775ec
...@@ -3,625 +3,883 @@ pragma solidity 0.7.6; ...@@ -3,625 +3,883 @@ pragma solidity 0.7.6;
import { IPreimageOracle } from "./interfaces/IPreimageOracle.sol"; import { IPreimageOracle } from "./interfaces/IPreimageOracle.sol";
// https://inst.eecs.berkeley.edu/~cs61c/resources/MIPS_Green_Sheet.pdf /// @title MIPS
// https://uweb.engr.arizona.edu/~ece369/Resources/spim/MIPSReference.pdf /// @notice The MIPS contract emulates a single MIPS instruction.
// https://en.wikibooks.org/wiki/MIPS_Assembly/Instruction_Formats /// Note that delay slots are isolated instructions:
/// the nextPC in the state pre-schedules where the VM jumps next.
// https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf /// The Step input is a packed VM state, with binary-merkle-tree
// page A-177 /// witness data for memory reads/writes.
/// The Step outputs a keccak256 hash of the packed VM State,
// MIPS linux kernel errors used by Go runtime: /// and logs the resulting state for offchain usage.
// https://github.com/golang/go/blob/master/src/syscall/zerrors_linux_mips.go /// @dev https://inst.eecs.berkeley.edu/~cs61c/resources/MIPS_Green_Sheet.pdf
/// @dev https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf
// This MIPS contract emulates a single MIPS instruction. /// (page A-177)
// /// @dev https://uweb.engr.arizona.edu/~ece369/Resources/spim/MIPSReference.pdf
// Note that delay slots are isolated instructions: /// @dev https://en.wikibooks.org/wiki/MIPS_Assembly/Instruction_Formats
// the nextPC in the state pre-schedules where the VM jumps next. /// @dev https://github.com/golang/go/blob/master/src/syscall/zerrors_linux_mips.go
// /// MIPS linux kernel errors used by Go runtime
// The Step input is a packed VM state, with binary-merkle-tree witness data for memory reads/writes.
// The Step outputs a keccak256 hash of the packed VM State, and logs the resulting state for offchain usage.
contract MIPS { contract MIPS {
struct State { /// @notice Stores the VM state.
bytes32 memRoot; /// Total state size: 32 + 32 + 6 * 4 + 1 + 1 + 8 + 32 * 4 = 226 bytes
bytes32 preimageKey; /// If nextPC != pc + 4, then the VM is executing a branch/jump delay slot.
uint32 preimageOffset; struct State {
uint32 pc; bytes32 memRoot;
uint32 nextPC; // State is executing a branch/jump delay slot if nextPC != pc+4 bytes32 preimageKey;
uint32 lo; uint32 preimageOffset;
uint32 hi; uint32 pc;
uint32 heap; uint32 nextPC;
uint8 exitCode; uint32 lo;
bool exited; uint32 hi;
uint64 step; uint32 heap;
uint32[32] registers; uint8 exitCode;
} bool exited;
uint64 step;
// total State size: 32+32+6*4+1+1+8+32*4 = 226 bytes uint32[32] registers;
uint32 constant public BRK_START = 0x40000000;
uint32 constant FD_STDIN = 0;
uint32 constant FD_STDOUT = 1;
uint32 constant FD_STDERR = 2;
uint32 constant FD_HINT_READ = 3;
uint32 constant FD_HINT_WRITE = 4;
uint32 constant FD_PREIMAGE_READ = 5;
uint32 constant FD_PREIMAGE_WRITE = 6;
uint32 constant EBADF = 0x9;
uint32 constant EINVAL = 0x16;
IPreimageOracle public oracle;
function SE(uint32 dat, uint32 idx) internal pure returns (uint32) {
bool isSigned = (dat >> (idx-1)) != 0;
uint256 signed = ((1 << (32-idx)) - 1) << idx;
uint256 mask = (1 << idx) - 1;
return uint32(dat&mask | (isSigned ? signed : 0));
}
function outputState() internal returns (bytes32 out) {
assembly {
// copies 'size' bytes, right-aligned in word at 'from', to 'to', incl. trailing data
function copyMem(from, to, size) -> fromOut, toOut {
mstore(to, mload(add(from, sub(32, size))))
fromOut := add(from, 32)
toOut := add(to, size)
}
let from := 0x80 // state
let start := mload(0x40) // free mem ptr
let to := start
from, to := copyMem(from, to, 32) // memRoot
from, to := copyMem(from, to, 32) // preimageKey
from, to := copyMem(from, to, 4) // preimageOffset
from, to := copyMem(from, to, 4) // pc
from, to := copyMem(from, to, 4) // nextPC
from, to := copyMem(from, to, 4) // lo
from, to := copyMem(from, to, 4) // hi
from, to := copyMem(from, to, 4) // heap
from, to := copyMem(from, to, 1) // exitCode
from, to := copyMem(from, to, 1) // exited
from, to := copyMem(from, to, 8) // step
from := add(from, 32) // offset to registers
for { let i := 0 } lt(i, 32) { i := add(i, 1) } { from, to := copyMem(from, to, 4) } // registers
mstore(to, 0) // clean up end
log0(start, sub(to, start)) // log the resulting MIPS state, for debugging
out := keccak256(start, sub(to, start))
} }
return out;
}
function handleSyscall() internal returns (bytes32) { /// @notice Start of the data segment.
State memory state; uint32 constant public BRK_START = 0x40000000;
assembly {
state := 0x80 uint32 constant FD_STDIN = 0;
uint32 constant FD_STDOUT = 1;
uint32 constant FD_STDERR = 2;
uint32 constant FD_HINT_READ = 3;
uint32 constant FD_HINT_WRITE = 4;
uint32 constant FD_PREIMAGE_READ = 5;
uint32 constant FD_PREIMAGE_WRITE = 6;
uint32 constant EBADF = 0x9;
uint32 constant EINVAL = 0x16;
/// @notice The pre-image oracle.
IPreimageOracle public oracle;
/// @notice Extends the value leftwards with its most significant bit (sign extension).
function SE(uint32 dat, uint32 idx) internal pure returns (uint32) {
bool isSigned = (dat >> (idx - 1)) != 0;
uint256 signed = ((1 << (32 - idx)) - 1) << idx;
uint256 mask = (1 << idx) - 1;
return uint32(dat & mask | (isSigned ? signed : 0));
} }
uint32 syscall_no = state.registers[2];
uint32 v0 = 0; /// @notice Computes the hash of the MIPS state.
uint32 v1 = 0; /// @return out_ The hash of the MIPS state.
function outputState() internal returns (bytes32 out_) {
uint32 a0 = state.registers[4]; assembly {
uint32 a1 = state.registers[5]; // copies 'size' bytes, right-aligned in word at 'from', to 'to', incl. trailing data
uint32 a2 = state.registers[6]; function copyMem(from, to, size) -> fromOut, toOut {
mstore(to, mload(add(from, sub(32, size))))
if (syscall_no == 4090) { fromOut := add(from, 32)
// mmap toOut := add(to, size)
uint32 sz = a1; }
if (sz&4095 != 0) { // adjust size to align with page size
sz += 4096 - (sz&4095); // From points to the MIPS State
} let from := 0x80
if (a0 == 0) {
v0 = state.heap; // Copy to the free memory pointer
state.heap += sz; let start := mload(0x40)
} else { let to := start
v0 = a0;
} // Copy state to free memory
} else if (syscall_no == 4045) { from, to := copyMem(from, to, 32) // memRoot
// brk from, to := copyMem(from, to, 32) // preimageKey
v0 = BRK_START; from, to := copyMem(from, to, 4) // preimageOffset
} else if (syscall_no == 4120) { from, to := copyMem(from, to, 4) // pc
// clone (not supported) from, to := copyMem(from, to, 4) // nextPC
v0 = 1; from, to := copyMem(from, to, 4) // lo
} else if (syscall_no == 4246) { from, to := copyMem(from, to, 4) // hi
// exit group from, to := copyMem(from, to, 4) // heap
state.exited = true; from, to := copyMem(from, to, 1) // exitCode
state.exitCode = uint8(a0); from, to := copyMem(from, to, 1) // exited
return outputState(); from, to := copyMem(from, to, 8) // step
} else if (syscall_no == 4003) { // read from := add(from, 32) // offset to registers
// args: a0 = fd, a1 = addr, a2 = count
// returns: v0 = read, v1 = err code // Copy registers
if (a0 == FD_STDIN) { for { let i := 0 } lt(i, 32) { i := add(i, 1) } {
// leave v0 and v1 zero: read nothing, no error from, to := copyMem(from, to, 4)
} else if (a0 == FD_PREIMAGE_READ) { // pre-image oracle }
// verify proof 1 is correct, and get the existing memory.
uint32 mem = readMem(a1 & 0xFFffFFfc, 1); // mask the addr to align it to 4 bytes // Clean up end of memory
(bytes32 dat, uint256 datLen) = oracle.readPreimage(state.preimageKey, state.preimageOffset); mstore(to, 0)
assembly { // assembly for more precise ops, and no var count limit
let alignment := and(a1, 3) // the read might not start at an aligned address // Log the resulting MIPS state, for debugging
let space := sub(4, alignment) // remaining space in memory word log0(start, sub(to, start))
if lt(space, datLen) { datLen := space } // if less space than data, shorten data
if lt(a2, datLen) { datLen := a2 } // if requested to read less, read less // Compute the hash of the resulting MIPS state
dat := shr(sub(256, mul(datLen, 8)), dat) // right-align data out_ := keccak256(start, sub(to, start))
dat := shl(mul(add(sub(4, datLen), alignment), 8), dat) // position data to insert into memory word
let mask := sub(shl(mul(sub(4, alignment), 8), 1), 1) // mask all bytes after start
let suffixMask := sub(shl(mul(sub(sub(4, alignment), datLen), 8), 1), 1) // mask of all bytes starting from end, maybe none
mask := and(mask, not(suffixMask)) // reduce mask to just cover the data we insert
mem := or(and(mem, not(mask)), dat) // clear masked part of original memory, and insert data
}
writeMem(a1 & 0xFFffFFfc, 1, mem);
state.preimageOffset += uint32(datLen);
v0 = uint32(datLen);
} else if (a0 == FD_HINT_READ) { // hint response
// don't actually read into memory, just say we read it all, we ignore the result anyway
v0 = a2;
} else {
v0 = 0xFFffFFff;
v1 = EBADF;
}
} else if (syscall_no == 4004) { // write
// args: a0 = fd, a1 = addr, a2 = count
// returns: v0 = written, v1 = err code
if (a0 == FD_STDOUT || a0 == FD_STDERR || a0 == FD_HINT_WRITE) {
v0 = a2; // tell program we have written everything
} else if (a0 == FD_PREIMAGE_WRITE) { // pre-image oracle
uint32 mem = readMem(a1 & 0xFFffFFfc, 1); // mask the addr to align it to 4 bytes
bytes32 key = state.preimageKey;
assembly { // assembly for more precise ops, and no var count limit
let alignment := and(a1, 3) // the read might not start at an aligned address
let space := sub(4, alignment) // remaining space in memory word
if lt(space, a2) { a2 := space } // if less space than data, shorten data
key := shl(mul(a2, 8), key) // shift key, make space for new info
let mask := sub(shl(mul(a2, 8), 1), 1) // mask for extracting value from memory
mem := and(shr(mul(sub(space, a2), 8), mem), mask) // align value to right, mask it
key := or(key, mem) // insert into key
}
state.preimageKey = key;
state.preimageOffset = 0; // reset offset, to read new pre-image data from the start
v0 = a2;
} else {
v0 = 0xFFffFFff;
v1 = EBADF;
}
} else if (syscall_no == 4055) { // fcntl
// args: a0 = fd, a1 = cmd
if (a1 == 3) { // F_GETFL: get file descriptor flags
if (a0 == FD_STDIN || a0 == FD_PREIMAGE_READ || a0 == FD_HINT_READ) {
v0 = 0; // O_RDONLY
} else if (a0 == FD_STDOUT || a0 == FD_STDERR || a0 == FD_PREIMAGE_WRITE || a0 == FD_HINT_WRITE) {
v0 = 1; // O_WRONLY
} else {
v0 = 0xFFffFFff;
v1 = EBADF;
} }
} else { return out_;
v0 = 0xFFffFFff;
v1 = EINVAL; // cmd not recognized by this kernel
}
} }
state.registers[2] = v0; /// @notice Handles a syscall.
state.registers[7] = v1; function handleSyscall() internal returns (bytes32) {
// Load state from memory
State memory state;
assembly {
state := 0x80
}
state.pc = state.nextPC; uint32 syscall_no = state.registers[2];
state.nextPC = state.nextPC + 4; uint32 v0 = 0;
uint32 v1 = 0;
uint32 a0 = state.registers[4];
uint32 a1 = state.registers[5];
uint32 a2 = state.registers[6];
if (syscall_no == 4090) {
// mmap
uint32 sz = a1;
if (sz&4095 != 0) { // adjust size to align with page size
sz += 4096 - (sz&4095);
}
if (a0 == 0) {
v0 = state.heap;
state.heap += sz;
} else {
v0 = a0;
}
} else if (syscall_no == 4045) {
// brk
v0 = BRK_START;
} else if (syscall_no == 4120) {
// clone (not supported)
v0 = 1;
} else if (syscall_no == 4246) {
// exit group
state.exited = true;
state.exitCode = uint8(a0);
return outputState();
} else if (syscall_no == 4003) { // read
// args: a0 = fd, a1 = addr, a2 = count
// returns: v0 = read, v1 = err code
if (a0 == FD_STDIN) {
// leave v0 and v1 zero: read nothing, no error
} else if (a0 == FD_PREIMAGE_READ) { // pre-image oracle
// verify proof 1 is correct, and get the existing memory.
uint32 mem = readMem(a1 & 0xFFffFFfc, 1); // mask the addr to align it to 4 bytes
(bytes32 dat, uint256 datLen) = oracle.readPreimage(state.preimageKey, state.preimageOffset);
assembly { // assembly for more precise ops, and no var count limit
let alignment := and(a1, 3) // the read might not start at an aligned address
let space := sub(4, alignment) // remaining space in memory word
if lt(space, datLen) { datLen := space } // if less space than data, shorten data
if lt(a2, datLen) { datLen := a2 } // if requested to read less, read less
dat := shr(sub(256, mul(datLen, 8)), dat) // right-align data
dat := shl(mul(add(sub(4, datLen), alignment), 8), dat) // position data to insert into memory word
let mask := sub(shl(mul(sub(4, alignment), 8), 1), 1) // mask all bytes after start
let suffixMask := sub(shl(mul(sub(sub(4, alignment), datLen), 8), 1), 1) // mask of all bytes starting from end, maybe none
mask := and(mask, not(suffixMask)) // reduce mask to just cover the data we insert
mem := or(and(mem, not(mask)), dat) // clear masked part of original memory, and insert data
}
writeMem(a1 & 0xFFffFFfc, 1, mem);
state.preimageOffset += uint32(datLen);
v0 = uint32(datLen);
} else if (a0 == FD_HINT_READ) { // hint response
// don't actually read into memory, just say we read it all, we ignore the result anyway
v0 = a2;
} else {
v0 = 0xFFffFFff;
v1 = EBADF;
}
} else if (syscall_no == 4004) { // write
// args: a0 = fd, a1 = addr, a2 = count
// returns: v0 = written, v1 = err code
if (a0 == FD_STDOUT || a0 == FD_STDERR || a0 == FD_HINT_WRITE) {
v0 = a2; // tell program we have written everything
} else if (a0 == FD_PREIMAGE_WRITE) { // pre-image oracle
uint32 mem = readMem(a1 & 0xFFffFFfc, 1); // mask the addr to align it to 4 bytes
bytes32 key = state.preimageKey;
assembly { // assembly for more precise ops, and no var count limit
let alignment := and(a1, 3) // the read might not start at an aligned address
let space := sub(4, alignment) // remaining space in memory word
if lt(space, a2) { a2 := space } // if less space than data, shorten data
key := shl(mul(a2, 8), key) // shift key, make space for new info
let mask := sub(shl(mul(a2, 8), 1), 1) // mask for extracting value from memory
mem := and(shr(mul(sub(space, a2), 8), mem), mask) // align value to right, mask it
key := or(key, mem) // insert into key
}
state.preimageKey = key;
state.preimageOffset = 0; // reset offset, to read new pre-image data from the start
v0 = a2;
} else {
v0 = 0xFFffFFff;
v1 = EBADF;
}
} else if (syscall_no == 4055) { // fcntl
// args: a0 = fd, a1 = cmd
if (a1 == 3) { // F_GETFL: get file descriptor flags
if (a0 == FD_STDIN || a0 == FD_PREIMAGE_READ || a0 == FD_HINT_READ) {
v0 = 0; // O_RDONLY
} else if (a0 == FD_STDOUT || a0 == FD_STDERR || a0 == FD_PREIMAGE_WRITE || a0 == FD_HINT_WRITE) {
v0 = 1; // O_WRONLY
} else {
v0 = 0xFFffFFff;
v1 = EBADF;
}
} else {
v0 = 0xFFffFFff;
v1 = EINVAL; // cmd not recognized by this kernel
}
}
return outputState(); state.registers[2] = v0;
} state.registers[7] = v1;
function handleBranch(uint32 opcode, uint32 insn, uint32 rtReg, uint32 rs) internal returns (bytes32) { state.pc = state.nextPC;
State memory state; state.nextPC = state.nextPC + 4;
assembly {
state := 0x80
}
bool shouldBranch = false;
if (opcode == 4 || opcode == 5) { // beq/bne
uint32 rt = state.registers[rtReg];
shouldBranch = (rs == rt && opcode == 4) || (rs != rt && opcode == 5);
} else if (opcode == 6) { shouldBranch = int32(rs) <= 0; // blez
} else if (opcode == 7) { shouldBranch = int32(rs) > 0; // bgtz
} else if (opcode == 1) {
// regimm
uint32 rtv = ((insn >> 16) & 0x1F);
if (rtv == 0) shouldBranch = int32(rs) < 0; // bltz
if (rtv == 1) shouldBranch = int32(rs) >= 0; // bgez
}
uint32 prevPC = state.pc; return outputState();
state.pc = state.nextPC; // execute the delay slot first
if (shouldBranch) {
state.nextPC = prevPC + 4 + (SE(insn&0xFFFF, 16)<<2); // then continue with the instruction the branch jumps to.
} else {
state.nextPC = state.nextPC + 4; // branch not taken
} }
return outputState(); /// @notice Handles a branch instruction, updating the MIPS state PC where needed.
} /// @param _opcode The opcode of the branch instruction.
/// @param _insn The instruction to be executed.
/// @param _rtReg The register to be used for the branch.
/// @param _rs The register to be compared with the branch register.
/// @return out_ The hashed MIPS state.
function handleBranch(uint32 _opcode, uint32 _insn, uint32 _rtReg, uint32 _rs) internal returns (bytes32 out_) {
// Load state from memory
State memory state;
assembly {
state := 0x80
}
function handleHiLo(uint32 func, uint32 rs, uint32 rt, uint32 storeReg) internal returns (bytes32) { bool shouldBranch = false;
State memory state;
assembly {
state := 0x80
}
uint32 val;
if (func == 0x10) val = state.hi; // mfhi
else if (func == 0x11) state.hi = rs; // mthi
else if (func == 0x12) val = state.lo; // mflo
else if (func == 0x13) state.lo = rs; // mtlo
else if (func == 0x18) { // mult
uint64 acc = uint64(int64(int32(rs))*int64(int32(rt)));
state.hi = uint32(acc>>32);
state.lo = uint32(acc);
} else if (func == 0x19) { // multu
uint64 acc = uint64(uint64(rs)*uint64(rt));
state.hi = uint32(acc>>32);
state.lo = uint32(acc);
} else if (func == 0x1a) { // div
state.hi = uint32(int32(rs)%int32(rt));
state.lo = uint32(int32(rs)/int32(rt));
} else if (func == 0x1b) { // divu
state.hi = rs%rt;
state.lo = rs/rt;
}
if (storeReg != 0) { // beq/bne: Branch on equal / not equal
state.registers[storeReg] = val; if (_opcode == 4 || _opcode == 5) {
} uint32 rt = state.registers[_rtReg];
shouldBranch = (_rs == rt && _opcode == 4) || (_rs != rt && _opcode == 5);
}
// blez: Branches if instruction is less than or equal to zero
else if (_opcode == 6) {
shouldBranch = int32(_rs) <= 0;
}
// bgtz: Branches if instruction is greater than zero
else if (_opcode == 7) {
shouldBranch = int32(_rs) > 0;
}
// bltz/bgez: Branch on less than zero / greater than or equal to zero
else if (_opcode == 1) {
// regimm
uint32 rtv = ((_insn >> 16) & 0x1F);
if (rtv == 0) {
shouldBranch = int32(_rs) < 0;
}
if (rtv == 1) {
shouldBranch = int32(_rs) >= 0;
}
}
state.pc = state.nextPC; // Update the state's previous PC
state.nextPC = state.nextPC + 4; uint32 prevPC = state.pc;
return outputState(); // Execute the delay slot first
} state.pc = state.nextPC;
function handleJump(uint32 linkReg, uint32 dest) internal returns (bytes32) { // If we should branch, update the PC to the branch target
State memory state; // Otherwise, proceed to the next instruction
assembly { if (shouldBranch) {
state := 0x80 state.nextPC = prevPC + 4 + (SE(_insn & 0xFFFF, 16) << 2);
} } else {
uint32 prevPC = state.pc; state.nextPC = state.nextPC + 4;
state.pc = state.nextPC; }
state.nextPC = dest;
if (linkReg != 0) {
state.registers[linkReg] = prevPC+8; // set the link-register to the instr after the delay slot instruction.
}
return outputState();
}
function handleRd(uint32 storeReg, uint32 val, bool conditional) internal returns (bytes32) { // Return the hash of the resulting state
State memory state; out_ = outputState();
assembly {
state := 0x80
}
require(storeReg < 32, "valid register");
// never write to reg 0, and it can be conditional (movz, movn)
if (storeReg != 0 && conditional) {
state.registers[storeReg] = val;
} }
state.pc = state.nextPC; /// @notice Handles HI and LO register instructions.
state.nextPC = state.nextPC + 4; /// @param _func The function code of the instruction.
/// @param _rs The value of the RS register.
return outputState(); /// @param _rt The value of the RT register.
} /// @param _storeReg The register to store the result in.
/// @return out_ The hash of the resulting MIPS state.
function proofOffset(uint8 proofIndex) internal pure returns (uint256 offset) { function handleHiLo(uint32 _func, uint32 _rs, uint32 _rt, uint32 _storeReg) internal returns (bytes32 out_) {
// A proof of 32 bit memory, with 32-byte leaf values, is (32-5)=27 bytes32 entries. // Load state from memory
// And the leaf value itself needs to be encoded as well. And proof.offset == 358 State memory state;
offset = 358 + (uint256(proofIndex) * (28*32)); assembly {
uint256 s = 0; state := 0x80
assembly { s := calldatasize() } }
require(s >= (offset + 28*32), "check that there is enough calldata");
return offset; uint32 val;
}
// mfhi: Move the contents of the HI register into the destination
function readMem(uint32 addr, uint8 proofIndex) internal pure returns (uint32 out) { if (_func == 0x10) {
uint256 offset = proofOffset(proofIndex); val = state.hi;
assembly { }
if and(addr, 3) { revert(0, 0) } // quick addr alignment check // mthi: Move the contents of the source into the HI register
let leaf := calldataload(offset) else if (_func == 0x11) {
offset := add(offset, 32) state.hi = _rs;
function hashPair(a, b) -> h { }
mstore(0, a) // use scratch space slots to hash the two nodes together // mflo: Move the contents of the LO register into the destination
mstore(32, b) else if (_func == 0x12) {
h := keccak256(0, 64) val = state.lo;
} }
let path := shr(5, addr) // mtlo: Move the contents of the source into the LO register
let node := leaf // starting from the leaf node, work back up by combining with siblings, to reconstruct the root else if (_func == 0x13) {
for { let i := 0 } lt(i, 27) { i := add(i, 1) } { state.lo = _rs;
let sibling := calldataload(offset) }
offset := add(offset, 32) // mult: Multiplies `rs` by `rt` and stores the result in HI and LO registers
switch and(shr(i, path), 1) else if (_func == 0x18) {
case 0 { node := hashPair(node, sibling) } uint64 acc = uint64(int64(int32(_rs)) * int64(int32(_rt)));
case 1 { node := hashPair(sibling, node) } state.hi = uint32(acc >> 32);
} state.lo = uint32(acc);
let memRoot := mload(0x80) // load memRoot, first field of state }
if iszero(eq(node, memRoot)) { // verify the root matches // multu: Unsigned multiplies `rs` by `rt` and stores the result in HI and LO registers
mstore(0, 0x0badf00d) else if (_func == 0x19) {
revert(0, 32) uint64 acc = uint64(uint64(_rs) * uint64(_rt));
} state.hi = uint32(acc >> 32);
// bits to shift = (32 - 4 - (addr % 32)) * 8 state.lo = uint32(acc);
let shamt := shl(3, sub(sub(32, 4), and(addr, 31))) }
out := and(shr(shamt, leaf), 0xFFffFFff) // div: Divides `rs` by `rt`.
} // Stores the quotient in LO
return out; // And the remainder in HI
} else if (_func == 0x1a) {
state.hi = uint32(int32(_rs) % int32(_rt));
// writeMem writes the value by first overwriting the part of the leaf, and then recomputing the memory merkle root. state.lo = uint32(int32(_rs) / int32(_rt));
function writeMem(uint32 addr, uint8 proofIndex, uint32 value) internal pure { }
uint256 offset = proofOffset(proofIndex); // divu: Unsigned divides `rs` by `rt`.
assembly { // Stores the quotient in LO
if and(addr, 3) { revert(0, 0) } // quick addr alignment check // And the remainder in HI
let leaf := calldataload(offset) else if (_func == 0x1b) {
let shamt := shl(3, sub(sub(32, 4), and(addr, 31))) state.hi = _rs % _rt;
// mask out 4 bytes, and OR in the value state.lo = _rs / _rt;
leaf := or(and(leaf, not(shl(shamt, 0xFFffFFff))), shl(shamt, value)) }
offset := add(offset, 32)
function hashPair(a, b) -> h {
mstore(0, a) // use scratch space slots to hash the two nodes together
mstore(32, b)
h := keccak256(0, 64)
}
let path := shr(5, addr)
let node := leaf // starting from the leaf node, work back up by combining with siblings, to reconstruct the root
for { let i := 0 } lt(i, 27) { i := add(i, 1) } {
let sibling := calldataload(offset)
offset := add(offset, 32)
switch and(shr(i, path), 1)
case 0 { node := hashPair(node, sibling) }
case 1 { node := hashPair(sibling, node) }
}
mstore(0x80, node) // store new memRoot, first field of state
}
}
// will revert if any required input state is missing
function step(bytes calldata stateData, bytes calldata proof) public returns (bytes32) {
State memory state;
// packed data is ~6 times smaller
assembly {
if iszero(eq(state, 0x80)) { // expected state mem offset check
revert(0,0)
}
if iszero(eq(mload(0x40), mul(32, 48))) { // expected memory check
revert(0,0)
}
if iszero(eq(stateData.offset, 100)) { // 32*3+4=100 expected state data offset
revert(0,0)
}
if iszero(eq(proof.offset, 358)) { // 100+32+226=358 expected proof offset
revert(0,0)
}
function putField(callOffset, memOffset, size) -> callOffsetOut, memOffsetOut {
// calldata is packed, thus starting left-aligned, shift-right to pad and right-align
let w := shr(shl(3, sub(32, size)), calldataload(callOffset))
mstore(memOffset, w)
callOffsetOut := add(callOffset, size)
memOffsetOut := add(memOffset, 32)
}
let c := stateData.offset // calldata offset
let m := 0x80 // mem offset
c, m := putField(c, m, 32) // memRoot
c, m := putField(c, m, 32) // preimageKey
c, m := putField(c, m, 4) // preimageOffset
c, m := putField(c, m, 4) // pc
c, m := putField(c, m, 4) // nextPC
c, m := putField(c, m, 4) // lo
c, m := putField(c, m, 4) // hi
c, m := putField(c, m, 4) // heap
c, m := putField(c, m, 1) // exitCode
c, m := putField(c, m, 1) // exited
c, m := putField(c, m, 8) // step
mstore(m, add(m, 32)) // offset to registers
m := add(m, 32)
for { let i := 0 } lt(i, 32) { i := add(i, 1) } { c, m := putField(c, m, 4) } // registers
}
if(state.exited) { // don't change state once exited
return outputState();
}
state.step += 1;
// instruction fetch // Store the result in the destination register, if applicable
uint32 insn = readMem(state.pc, 0); if (_storeReg != 0) {
state.registers[_storeReg] = val;
}
uint32 opcode = insn >> 26; // 6-bits // Update the PC
state.pc = state.nextPC;
state.nextPC = state.nextPC + 4;
// j-type j/jal // Return the hash of the resulting state
if (opcode == 2 || opcode == 3) { out_ = outputState();
// TODO(CLI-4136): likely bug in original code: MIPS spec says this should be in the "current" region;
// a 256 MB aligned region (i.e. use top 4 bits of branch delay slot (pc+4))
return handleJump(opcode == 2 ? 0 : 31, SE(insn&0x03FFFFFF, 26) << 2);
} }
// register fetch /// @notice Handles a jump instruction, updating the MIPS state PC where needed.
uint32 rs; // source register 1 value /// @param _linkReg The register to store the link to the instruction after the delay slot instruction.
uint32 rt; // source register 2 / temp value /// @param _dest The destination to jump to.
uint32 rtReg = (insn >> 16) & 0x1F; /// @return out_ The hashed MIPS state.
function handleJump(uint32 _linkReg, uint32 _dest) internal returns (bytes32 out_) {
// R-type or I-type (stores rt) // Load state from memory.
rs = state.registers[(insn >> 21) & 0x1F]; State memory state;
uint32 rdReg = rtReg; assembly {
if (opcode == 0 || opcode == 0x1c) { state := 0x80
// R-type (stores rd) }
rt = state.registers[rtReg];
rdReg = (insn >> 11) & 0x1F; // Update the next PC to the jump destination.
} else if (opcode < 0x20) { uint32 prevPC = state.pc;
// rt is SignExtImm state.pc = state.nextPC;
// don't sign extend for andi, ori, xori state.nextPC = _dest;
if (opcode == 0xC || opcode == 0xD || opcode == 0xe) {
// ZeroExtImm // Update the link-register to the instruction after the delay slot instruction.
rt = insn&0xFFFF; if (_linkReg != 0) {
} else { state.registers[_linkReg] = prevPC + 8;
// SignExtImm }
rt = SE(insn&0xFFFF, 16);
}
} else if (opcode >= 0x28 || opcode == 0x22 || opcode == 0x26) {
// store rt value with store
rt = state.registers[rtReg];
// store actual rt with lwl and lwr
rdReg = rtReg;
}
if ((opcode >= 4 && opcode < 8) || opcode == 1) { // Return the hash of the resulting state.
return handleBranch(opcode, insn, rtReg, rs); out_ = outputState();
} }
uint32 storeAddr = 0xFF_FF_FF_FF; /// @notice Handles a storing a value into a register.
// memory fetch (all I-type) /// @param _storeReg The register to store the value into.
// we do the load for stores also /// @param _val The value to store.
uint32 mem; /// @param _conditional Whether or not the store is conditional.
if (opcode >= 0x20) { /// @return out_ The hashed MIPS state.
// M[R[rs]+SignExtImm] function handleRd(uint32 _storeReg, uint32 _val, bool _conditional) internal returns (bytes32 out_) {
rs += SE(insn&0xFFFF, 16); // Load state from memory.
uint32 addr = rs & 0xFFFFFFFC; State memory state;
mem = readMem(addr, 1); assembly {
if (opcode >= 0x28 && opcode != 0x30) { state := 0x80
// store }
storeAddr = addr;
// store opcodes don't write back to a register // The destination register must be valid.
rdReg = 0; require(_storeReg < 32, "valid register");
}
// Never write to reg 0, and it can be conditional (movz, movn).
if (_storeReg != 0 && _conditional) {
state.registers[_storeReg] = _val;
}
// Update the PC.
state.pc = state.nextPC;
state.nextPC = state.nextPC + 4;
// Return the hash of the resulting state.
out_ = outputState();
} }
// ALU /// @notice Computes the offset of the proof in the calldata.
uint32 val = execute(insn, rs, rt, mem) & 0xffFFffFF; // swr outputs more than 4 bytes without the mask /// @param _proofIndex The index of the proof in the calldata.
/// @return offset_ The offset of the proof in the calldata.
uint32 func = insn & 0x3f; // 6-bits function proofOffset(uint8 _proofIndex) internal pure returns (uint256 offset_) {
if (opcode == 0 && func >= 8 && func < 0x1c) { // A proof of 32 bit memory, with 32-byte leaf values, is (32-5)=27 bytes32 entries.
if (func == 8 || func == 9) { // jr/jalr // And the leaf value itself needs to be encoded as well. And proof.offset == 358
return handleJump(func == 8 ? 0 : rdReg, rs); offset_ = 358 + (uint256(_proofIndex) * (28 * 32));
} uint256 s = 0;
assembly { s := calldatasize() }
if (func == 0xa) { // movz require(s >= (offset_ + 28 * 32), "check that there is enough calldata");
return handleRd(rdReg, rs, rt == 0); return offset_;
}
if (func == 0xb) { // movn
return handleRd(rdReg, rs, rt != 0);
}
// syscall (can read and write)
if (func == 0xC) {
return handleSyscall();
}
// lo and hi registers
// can write back
if (func >= 0x10 && func < 0x1c) {
return handleHiLo(func, rs, rt, rdReg);
}
} }
// stupid sc, write a 1 to rt /// @notice Reads a 32-bit value from memory.
if (opcode == 0x38 && rtReg != 0) { /// @param _addr The address to read from.
state.registers[rtReg] = 1; /// @param _proofIndex The index of the proof in the calldata.
/// @return out_ The hashed MIPS state.
function readMem(uint32 _addr, uint8 _proofIndex) internal pure returns (uint32 out_) {
// Compute the offset of the proof in the calldata.
uint256 offset = proofOffset(_proofIndex);
assembly {
// Validate the address alignement.
if and(_addr, 3) {
revert(0, 0)
}
// Load the leaf value.
let leaf := calldataload(offset)
offset := add(offset, 32)
// Convenience function to hash two nodes together in scratch space.
function hashPair(a, b) -> h {
mstore(0, a)
mstore(32, b)
h := keccak256(0, 64)
}
// Start with the leaf node.
// Work back up by combining with siblings, to reconstruct the root.
let path := shr(5, _addr)
let node := leaf
for { let i := 0 } lt(i, 27) { i := add(i, 1) } {
let sibling := calldataload(offset)
offset := add(offset, 32)
switch and(shr(i, path), 1)
case 0 {
node := hashPair(node, sibling)
} case 1 {
node := hashPair(sibling, node)
}
}
// Load the memory root from the first field of state.
let memRoot := mload(0x80)
// Verify the root matches.
if iszero(eq(node, memRoot)) {
mstore(0, 0x0badf00d)
revert(0, 32)
}
// Bits to shift = (32 - 4 - (addr % 32)) * 8
let shamt := shl(3, sub(sub(32, 4), and(_addr, 31)))
out_ := and(shr(shamt, leaf), 0xFFffFFff)
}
} }
// write memory /// @notice Writes a 32-bit value to memory.
if (storeAddr != 0xFF_FF_FF_FF) { /// This function first overwrites the part of the leaf.
writeMem(storeAddr, 1, val); /// Then it recomputes the memory merkle root.
/// @param _addr The address to write to.
/// @param _proofIndex The index of the proof in the calldata.
/// @param _val The value to write.
function writeMem(uint32 _addr, uint8 _proofIndex, uint32 _val) internal pure {
// Compute the offset of the proof in the calldata.
uint256 offset = proofOffset(_proofIndex);
assembly {
// Validate the address alignement.
if and(_addr, 3) {
revert(0, 0)
}
// Load the leaf value.
let leaf := calldataload(offset)
let shamt := shl(3, sub(sub(32, 4), and(_addr, 31)))
// Mask out 4 bytes, and OR in the value
leaf := or(and(leaf, not(shl(shamt, 0xFFffFFff))), shl(shamt, _val))
offset := add(offset, 32)
// Convenience function to hash two nodes together in scratch space.
function hashPair(a, b) -> h {
mstore(0, a)
mstore(32, b)
h := keccak256(0, 64)
}
// Start with the leaf node.
// Work back up by combining with siblings, to reconstruct the root.
let path := shr(5, _addr)
let node := leaf
for { let i := 0 } lt(i, 27) { i := add(i, 1) } {
let sibling := calldataload(offset)
offset := add(offset, 32)
switch and(shr(i, path), 1)
case 0 {
node := hashPair(node, sibling)
} case 1 {
node := hashPair(sibling, node)
}
}
// Store the new memory root in the first field of state.
mstore(0x80, node)
}
} }
// write back the value to destination register /// @notice Executes a single step of the vm.
return handleRd(rdReg, val, true); /// Will revert if any required input state is missing.
} function step(bytes calldata stateData, bytes calldata proof) public returns (bytes32) {
State memory state;
function execute(uint32 insn, uint32 rs, uint32 rt, uint32 mem) internal pure returns (uint32) {
uint32 opcode = insn >> 26; // 6-bits // Packed calldata is ~6 times smaller than state size
uint32 func = insn & 0x3f; // 6-bits assembly {
// TODO(CLI-4136): deref the immed into a register if iszero(eq(state, 0x80)) { // expected state mem offset check
revert(0,0)
if (opcode < 0x20) { }
// transform ArithLogI if iszero(eq(mload(0x40), mul(32, 48))) { // expected memory check
// TODO(CLI-4136): replace with table revert(0,0)
if (opcode >= 8 && opcode < 0xF) { }
if (opcode == 8) { func = 0x20; } // addi if iszero(eq(stateData.offset, 100)) { // 32*3+4=100 expected state data offset
else if (opcode == 9) { func = 0x21; } // addiu revert(0,0)
else if (opcode == 0xa) { func = 0x2a; } // slti }
else if (opcode == 0xb) { func = 0x2B; } // sltiu if iszero(eq(proof.offset, 358)) { // 100+32+226=358 expected proof offset
else if (opcode == 0xc) { func = 0x24; } // andi revert(0,0)
else if (opcode == 0xd) { func = 0x25; } // ori }
else if (opcode == 0xe) { func = 0x26; } // xori
opcode = 0; function putField(callOffset, memOffset, size) -> callOffsetOut, memOffsetOut {
} // calldata is packed, thus starting left-aligned, shift-right to pad and right-align
let w := shr(shl(3, sub(32, size)), calldataload(callOffset))
// 0 is opcode SPECIAL mstore(memOffset, w)
if (opcode == 0) { callOffsetOut := add(callOffset, size)
uint32 shamt = (insn >> 6) & 0x1f; memOffsetOut := add(memOffset, 32)
if (func < 0x20) { }
if (func >= 0x08) { return rs; // jr/jalr/div + others
// Shift and ShiftV // Unpack state from calldata into memory
} else if (func == 0x00) { return rt << shamt; // sll let c := stateData.offset // calldata offset
} else if (func == 0x02) { return rt >> shamt; // srl let m := 0x80 // mem offset
} else if (func == 0x03) { return SE(rt >> shamt, 32-shamt); // sra c, m := putField(c, m, 32) // memRoot
} else if (func == 0x04) { return rt << (rs&0x1F); // sllv c, m := putField(c, m, 32) // preimageKey
} else if (func == 0x06) { return rt >> (rs&0x1F); // srlv c, m := putField(c, m, 4) // preimageOffset
} else if (func == 0x07) { return SE(rt >> rs, 32-rs); // srav c, m := putField(c, m, 4) // pc
} c, m := putField(c, m, 4) // nextPC
} c, m := putField(c, m, 4) // lo
// 0x10-0x13 = mfhi, mthi, mflo, mtlo c, m := putField(c, m, 4) // hi
// R-type (ArithLog) c, m := putField(c, m, 4) // heap
if (func == 0x20 || func == 0x21) { return rs+rt; // add or addu c, m := putField(c, m, 1) // exitCode
} else if (func == 0x22 || func == 0x23) { return rs-rt; // sub or subu c, m := putField(c, m, 1) // exited
} else if (func == 0x24) { return rs&rt; // and c, m := putField(c, m, 8) // step
} else if (func == 0x25) { return (rs|rt); // or
} else if (func == 0x26) { return (rs^rt); // xor // Unpack register calldata into memory
} else if (func == 0x27) { return ~(rs|rt); // nor mstore(m, add(m, 32)) // offset to registers
} else if (func == 0x2a) { m := add(m, 32)
return int32(rs)<int32(rt) ? 1 : 0; // slt for { let i := 0 } lt(i, 32) { i := add(i, 1) } {
} else if (func == 0x2B) { c, m := putField(c, m, 4)
return rs<rt ? 1 : 0; // sltu }
} }
} else if (opcode == 0xf) { return rt<<16; // lui
} else if (opcode == 0x1c) { // SPECIAL2 // Don't change state once exited
if (func == 2) return uint32(int32(rs)*int32(rt)); // mul if (state.exited) {
if (func == 0x20 || func == 0x21) { // clo return outputState();
if (func == 0x20) rs = ~rs; }
uint32 i = 0; while (rs&0x80000000 != 0) { i++; rs <<= 1; } return i;
} state.step += 1;
}
} else if (opcode < 0x28) { // instruction fetch
if (opcode == 0x20) { // lb uint32 insn = readMem(state.pc, 0);
return SE((mem >> (24-(rs&3)*8)) & 0xFF, 8); uint32 opcode = insn >> 26; // 6-bits
} else if (opcode == 0x21) { // lh
return SE((mem >> (16-(rs&2)*8)) & 0xFFFF, 16); // j-type j/jal
} else if (opcode == 0x22) { // lwl if (opcode == 2 || opcode == 3) {
uint32 val = mem << ((rs&3)*8); // TODO(CLI-4136): likely bug in original code: MIPS spec says this should be in the "current" region;
uint32 mask = uint32(0xFFFFFFFF) << ((rs&3)*8); // a 256 MB aligned region (i.e. use top 4 bits of branch delay slot (pc+4))
return (rt & ~mask) | val; return handleJump(opcode == 2 ? 0 : 31, SE(insn & 0x03FFFFFF, 26) << 2);
} else if (opcode == 0x23) { return mem; // lw }
} else if (opcode == 0x24) { // lbu
return (mem >> (24-(rs&3)*8)) & 0xFF; // register fetch
} else if (opcode == 0x25) { // lhu uint32 rs; // source register 1 value
return (mem >> (16-(rs&2)*8)) & 0xFFFF; uint32 rt; // source register 2 / temp value
} else if (opcode == 0x26) { // lwr uint32 rtReg = (insn >> 16) & 0x1F;
uint32 val = mem >> (24-(rs&3)*8);
uint32 mask = uint32(0xFFFFFFFF) >> (24-(rs&3)*8); // R-type or I-type (stores rt)
return (rt & ~mask) | val; rs = state.registers[(insn >> 21) & 0x1F];
} uint32 rdReg = rtReg;
} else if (opcode == 0x28) { // sb
uint32 val = (rt&0xFF) << (24-(rs&3)*8); if (opcode == 0 || opcode == 0x1c) {
uint32 mask = 0xFFFFFFFF ^ uint32(0xFF << (24-(rs&3)*8)); // R-type (stores rd)
return (mem & mask) | val; rt = state.registers[rtReg];
} else if (opcode == 0x29) { // sh rdReg = (insn >> 11) & 0x1F;
uint32 val = (rt&0xFFFF) << (16-(rs&2)*8); } else if (opcode < 0x20) {
uint32 mask = 0xFFFFFFFF ^ uint32(0xFFFF << (16-(rs&2)*8)); // rt is SignExtImm
return (mem & mask) | val; // don't sign extend for andi, ori, xori
} else if (opcode == 0x2a) { // swl if (opcode == 0xC || opcode == 0xD || opcode == 0xe) {
uint32 val = rt >> ((rs&3)*8); // ZeroExtImm
uint32 mask = uint32(0xFFFFFFFF) >> ((rs&3)*8); rt = insn & 0xFFFF;
return (mem & ~mask) | val; } else {
} else if (opcode == 0x2b) { // sw // SignExtImm
return rt; rt = SE(insn & 0xFFFF, 16);
} else if (opcode == 0x2e) { // swr }
uint32 val = rt << (24-(rs&3)*8); } else if (opcode >= 0x28 || opcode == 0x22 || opcode == 0x26) {
uint32 mask = uint32(0xFFFFFFFF) << (24-(rs&3)*8); // store rt value with store
return (mem & ~mask) | val; rt = state.registers[rtReg];
} else if (opcode == 0x30) { return mem; // ll
} else if (opcode == 0x38) { return rt; // sc // store actual rt with lwl and lwr
rdReg = rtReg;
}
if ((opcode >= 4 && opcode < 8) || opcode == 1) {
return handleBranch(opcode, insn, rtReg, rs);
}
uint32 storeAddr = 0xFF_FF_FF_FF;
// memory fetch (all I-type)
// we do the load for stores also
uint32 mem;
if (opcode >= 0x20) {
// M[R[rs]+SignExtImm]
rs += SE(insn&0xFFFF, 16);
uint32 addr = rs & 0xFFFFFFFC;
mem = readMem(addr, 1);
if (opcode >= 0x28 && opcode != 0x30) {
// store
storeAddr = addr;
// store opcodes don't write back to a register
rdReg = 0;
}
}
// ALU
uint32 val = execute(insn, rs, rt, mem) & 0xffFFffFF; // swr outputs more than 4 bytes without the mask
uint32 func = insn & 0x3f; // 6-bits
if (opcode == 0 && func >= 8 && func < 0x1c) {
if (func == 8 || func == 9) { // jr/jalr
return handleJump(func == 8 ? 0 : rdReg, rs);
}
if (func == 0xa) { // movz
return handleRd(rdReg, rs, rt == 0);
}
if (func == 0xb) { // movn
return handleRd(rdReg, rs, rt != 0);
}
// syscall (can read and write)
if (func == 0xC) {
return handleSyscall();
}
// lo and hi registers
// can write back
if (func >= 0x10 && func < 0x1c) {
return handleHiLo(func, rs, rt, rdReg);
}
}
// stupid sc, write a 1 to rt
if (opcode == 0x38 && rtReg != 0) {
state.registers[rtReg] = 1;
}
// write memory
if (storeAddr != 0xFF_FF_FF_FF) {
writeMem(storeAddr, 1, val);
}
// write back the value to destination register
return handleRd(rdReg, val, true);
} }
revert("invalid instruction"); /// @notice Execute an instruction.
} function execute(uint32 insn, uint32 rs, uint32 rt, uint32 mem) internal pure returns (uint32) {
uint32 opcode = insn >> 26; // 6-bits
uint32 func = insn & 0x3f; // 6-bits
// TODO(CLI-4136): deref the immed into a register
if (opcode < 0x20) {
// transform ArithLogI
// TODO(CLI-4136): replace with table
if (opcode >= 8 && opcode < 0xF) {
if (opcode == 8) { func = 0x20; } // addi
else if (opcode == 9) { func = 0x21; } // addiu
else if (opcode == 0xa) { func = 0x2a; } // slti
else if (opcode == 0xb) { func = 0x2B; } // sltiu
else if (opcode == 0xc) { func = 0x24; } // andi
else if (opcode == 0xd) { func = 0x25; } // ori
else if (opcode == 0xe) { func = 0x26; } // xori
opcode = 0;
}
// 0 is opcode SPECIAL
if (opcode == 0) {
uint32 shamt = (insn >> 6) & 0x1f;
if (func < 0x20) {
// jr/jalr/div + others
if (func >= 0x08) {
return rs;
}
// sll: Logical Shift Left
else if (func == 0x00) {
return rt << shamt;
}
// srl: Logical Shift Right
else if (func == 0x02) {
return rt >> shamt;
}
// sra: Arithmetic Shift Right
else if (func == 0x03) {
return SE(rt >> shamt, 32 - shamt);
}
// sllv: Variable Logical Shift Left
else if (func == 0x04) {
return rt << (rs & 0x1F);
}
// srlv: Variable Logical Shift Right
else if (func == 0x06) {
return rt >> (rs & 0x1F);
}
// srav: Variable Arithmetic Shift Right
else if (func == 0x07) {
return SE(rt >> rs, 32 - rs);
}
}
// R-type (ArithLog)
// 0x10-0x13 = mfhi, mthi, mflo, mtlo
// add or addu
if (func == 0x20 || func == 0x21) {
return rs + rt;
}
// sub or subu
else if (func == 0x22 || func == 0x23) {
return rs - rt;
}
// and
else if (func == 0x24) {
return rs & rt;
}
// or
else if (func == 0x25) {
return (rs | rt);
}
// xor
else if (func == 0x26) {
return (rs ^ rt);
}
// nor
else if (func == 0x27) {
return ~(rs | rt);
}
// slt: Set to 1 if less than
else if (func == 0x2a) {
return int32(rs) < int32(rt) ? 1 : 0;
}
// sltu: Set to 1 if less than unsigned
else if (func == 0x2B) {
return rs<rt ? 1 : 0;
}
}
// lui: Load Upper Immediate
else if (opcode == 0xf) {
return rt << 16;
}
// SPECIAL2
else if (opcode == 0x1c) {
// mul
if (func == 2) {
return uint32(int32(rs) * int32(rt));
}
// clo
if (func == 0x20 || func == 0x21) {
if (func == 0x20) {
rs = ~rs;
}
uint32 i = 0;
while (rs&0x80000000 != 0) {
i++;
rs <<= 1;
}
return i;
}
}
}
else if (opcode < 0x28) {
// lb
if (opcode == 0x20) {
return SE((mem >> (24 - (rs & 3) * 8)) & 0xFF, 8);
}
// lh
else if (opcode == 0x21) {
return SE((mem >> (16 - (rs & 2) * 8)) & 0xFFFF, 16);
}
// lwl
else if (opcode == 0x22) {
uint32 val = mem << ((rs & 3) * 8);
uint32 mask = uint32(0xFFFFFFFF) << ((rs & 3) * 8);
return (rt & ~mask) | val;
}
// lw
else if (opcode == 0x23) {
return mem;
}
// lbu
else if (opcode == 0x24) {
return (mem >> (24 - (rs & 3) * 8)) & 0xFF;
}
// lhu
else if (opcode == 0x25) {
return (mem >> (16 - (rs & 2) * 8)) & 0xFFFF;
}
// lwr
else if (opcode == 0x26) {
uint32 val = mem >> (24 - (rs & 3) * 8);
uint32 mask = uint32(0xFFFFFFFF) >> (24 - (rs & 3) * 8);
return (rt & ~mask) | val;
}
}
// sb
else if (opcode == 0x28) {
uint32 val = (rt & 0xFF) << (24 - (rs & 3) * 8);
uint32 mask = 0xFFFFFFFF ^ uint32(0xFF << (24 - (rs & 3) * 8));
return (mem & mask) | val;
}
// sh
else if (opcode == 0x29) {
uint32 val = (rt & 0xFFFF) << (16 - (rs & 2) * 8);
uint32 mask = 0xFFFFFFFF ^ uint32(0xFFFF << (16 - (rs & 2) * 8));
return (mem & mask) | val;
}
// swl
else if (opcode == 0x2a) {
uint32 val = rt >> ((rs & 3) * 8);
uint32 mask = uint32(0xFFFFFFFF) >> ((rs & 3) * 8);
return (mem & ~mask) | val;
}
// sw
else if (opcode == 0x2b) {
return rt;
}
// swr
else if (opcode == 0x2e) {
uint32 val = rt << (24 - (rs & 3) * 8);
uint32 mask = uint32(0xFFFFFFFF) << (24 - (rs & 3) * 8);
return (mem & ~mask) | val;
}
// ll
else if (opcode == 0x30) {
return mem;
}
// sc
else if (opcode == 0x38) {
return rt;
}
revert("invalid instruction");
}
} }
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