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Commit d29775ec authored by refcell.eth's avatar refcell.eth Committed by GitHub
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Inline-comment documentation for MIPS.sol and styling. (#6276)

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op-bindings/bindings/mips.go
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...@@ -31,7 +31,7 @@ var ( ...@@ -31,7 +31,7 @@ var (
// MIPSMetaData contains all meta data concerning the MIPS contract. // MIPSMetaData contains all meta data concerning the MIPS contract.
var MIPSMetaData = &bind.MetaData{ var MIPSMetaData = &bind.MetaData{
ABI: "[{\"inputs\":[],\"name\":\"BRK_START\",\"outputs\":[{\"internalType\":\"uint32\",\"name\":\"\",\"type\":\"uint32\"}],\"stateMutability\":\"view\",\"type\":\"function\"},{\"inputs\":[],\"name\":\"oracle\",\"outputs\":[{\"internalType\":\"contractIPreimageOracle\",\"name\":\"\",\"type\":\"address\"}],\"stateMutability\":\"view\",\"type\":\"function\"},{\"inputs\":[{\"internalType\":\"bytes\",\"name\":\"stateData\",\"type\":\"bytes\"},{\"internalType\":\"bytes\",\"name\":\"proof\",\"type\":\"bytes\"}],\"name\":\"step\",\"outputs\":[{\"internalType\":\"bytes32\",\"name\":\"\",\"type\":\"bytes32\"}],\"stateMutability\":\"nonpayable\",\"type\":\"function\"}]", ABI: "[{\"inputs\":[],\"name\":\"BRK_START\",\"outputs\":[{\"internalType\":\"uint32\",\"name\":\"\",\"type\":\"uint32\"}],\"stateMutability\":\"view\",\"type\":\"function\"},{\"inputs\":[],\"name\":\"oracle\",\"outputs\":[{\"internalType\":\"contractIPreimageOracle\",\"name\":\"\",\"type\":\"address\"}],\"stateMutability\":\"view\",\"type\":\"function\"},{\"inputs\":[{\"internalType\":\"bytes\",\"name\":\"stateData\",\"type\":\"bytes\"},{\"internalType\":\"bytes\",\"name\":\"proof\",\"type\":\"bytes\"}],\"name\":\"step\",\"outputs\":[{\"internalType\":\"bytes32\",\"name\":\"\",\"type\":\"bytes32\"}],\"stateMutability\":\"nonpayable\",\"type\":\"function\"}]",
Bin: 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} }
// MIPSABI is the input ABI used to generate the binding from. // MIPSABI is the input ABI used to generate the binding from.
......
op-bindings/bindings/mips_more.go
View file @ d29775ec
...@@ -13,9 +13,9 @@ const MIPSStorageLayoutJSON = "{\"storage\":[{\"astId\":1000,\"contract\":\"cont ...@@ -13,9 +13,9 @@ const MIPSStorageLayoutJSON = "{\"storage\":[{\"astId\":1000,\"contract\":\"cont
var MIPSStorageLayout = new(solc.StorageLayout) var MIPSStorageLayout = new(solc.StorageLayout)
var MIPSDeployedBin = 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func init() { func init() {
if err := json.Unmarshal([]byte(MIPSStorageLayoutJSON), MIPSStorageLayout); err != nil { if err := json.Unmarshal([]byte(MIPSStorageLayoutJSON), MIPSStorageLayout); err != nil {
......
packages/contracts-bedrock/contracts/cannon/MIPS.sol
View file @ d29775ec
...@@ -3,31 +3,32 @@ pragma solidity 0.7.6; ...@@ -3,31 +3,32 @@ pragma solidity 0.7.6;
import { IPreimageOracle } from "./interfaces/IPreimageOracle.sol"; import { IPreimageOracle } from "./interfaces/IPreimageOracle.sol";
// https://inst.eecs.berkeley.edu/~cs61c/resources/MIPS_Green_Sheet.pdf /// @title MIPS
// https://uweb.engr.arizona.edu/~ece369/Resources/spim/MIPSReference.pdf /// @notice The MIPS contract emulates a single MIPS instruction.
// https://en.wikibooks.org/wiki/MIPS_Assembly/Instruction_Formats /// Note that delay slots are isolated instructions:
/// the nextPC in the state pre-schedules where the VM jumps next.
// https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf /// The Step input is a packed VM state, with binary-merkle-tree
// page A-177 /// witness data for memory reads/writes.
/// The Step outputs a keccak256 hash of the packed VM State,
// MIPS linux kernel errors used by Go runtime: /// and logs the resulting state for offchain usage.
// https://github.com/golang/go/blob/master/src/syscall/zerrors_linux_mips.go /// @dev https://inst.eecs.berkeley.edu/~cs61c/resources/MIPS_Green_Sheet.pdf
/// @dev https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf
// This MIPS contract emulates a single MIPS instruction. /// (page A-177)
// /// @dev https://uweb.engr.arizona.edu/~ece369/Resources/spim/MIPSReference.pdf
// Note that delay slots are isolated instructions: /// @dev https://en.wikibooks.org/wiki/MIPS_Assembly/Instruction_Formats
// the nextPC in the state pre-schedules where the VM jumps next. /// @dev https://github.com/golang/go/blob/master/src/syscall/zerrors_linux_mips.go
// /// MIPS linux kernel errors used by Go runtime
// The Step input is a packed VM state, with binary-merkle-tree witness data for memory reads/writes.
// The Step outputs a keccak256 hash of the packed VM State, and logs the resulting state for offchain usage.
contract MIPS { contract MIPS {
/// @notice Stores the VM state.
/// Total state size: 32 + 32 + 6 * 4 + 1 + 1 + 8 + 32 * 4 = 226 bytes
/// If nextPC != pc + 4, then the VM is executing a branch/jump delay slot.
struct State { struct State {
bytes32 memRoot; bytes32 memRoot;
bytes32 preimageKey; bytes32 preimageKey;
uint32 preimageOffset; uint32 preimageOffset;
uint32 pc; uint32 pc;
uint32 nextPC; // State is executing a branch/jump delay slot if nextPC != pc+4 uint32 nextPC;
uint32 lo; uint32 lo;
uint32 hi; uint32 hi;
uint32 heap; uint32 heap;
...@@ -37,8 +38,7 @@ contract MIPS { ...@@ -37,8 +38,7 @@ contract MIPS {
uint32[32] registers; uint32[32] registers;
} }
// total State size: 32+32+6*4+1+1+8+32*4 = 226 bytes /// @notice Start of the data segment.
uint32 constant public BRK_START = 0x40000000; uint32 constant public BRK_START = 0x40000000;
uint32 constant FD_STDIN = 0; uint32 constant FD_STDIN = 0;
...@@ -52,16 +52,20 @@ contract MIPS { ...@@ -52,16 +52,20 @@ contract MIPS {
uint32 constant EBADF = 0x9; uint32 constant EBADF = 0x9;
uint32 constant EINVAL = 0x16; uint32 constant EINVAL = 0x16;
/// @notice The pre-image oracle.
IPreimageOracle public oracle; IPreimageOracle public oracle;
/// @notice Extends the value leftwards with its most significant bit (sign extension).
function SE(uint32 dat, uint32 idx) internal pure returns (uint32) { function SE(uint32 dat, uint32 idx) internal pure returns (uint32) {
bool isSigned = (dat >> (idx-1)) != 0; bool isSigned = (dat >> (idx - 1)) != 0;
uint256 signed = ((1 << (32-idx)) - 1) << idx; uint256 signed = ((1 << (32 - idx)) - 1) << idx;
uint256 mask = (1 << idx) - 1; uint256 mask = (1 << idx) - 1;
return uint32(dat&mask | (isSigned ? signed : 0)); return uint32(dat & mask | (isSigned ? signed : 0));
} }
function outputState() internal returns (bytes32 out) { /// @notice Computes the hash of the MIPS state.
/// @return out_ The hash of the MIPS state.
function outputState() internal returns (bytes32 out_) {
assembly { assembly {
// copies 'size' bytes, right-aligned in word at 'from', to 'to', incl. trailing data // copies 'size' bytes, right-aligned in word at 'from', to 'to', incl. trailing data
function copyMem(from, to, size) -> fromOut, toOut { function copyMem(from, to, size) -> fromOut, toOut {
...@@ -69,9 +73,15 @@ contract MIPS { ...@@ -69,9 +73,15 @@ contract MIPS {
fromOut := add(from, 32) fromOut := add(from, 32)
toOut := add(to, size) toOut := add(to, size)
} }
let from := 0x80 // state
let start := mload(0x40) // free mem ptr // From points to the MIPS State
let from := 0x80
// Copy to the free memory pointer
let start := mload(0x40)
let to := start let to := start
// Copy state to free memory
from, to := copyMem(from, to, 32) // memRoot from, to := copyMem(from, to, 32) // memRoot
from, to := copyMem(from, to, 32) // preimageKey from, to := copyMem(from, to, 32) // preimageKey
from, to := copyMem(from, to, 4) // preimageOffset from, to := copyMem(from, to, 4) // preimageOffset
...@@ -84,19 +94,32 @@ contract MIPS { ...@@ -84,19 +94,32 @@ contract MIPS {
from, to := copyMem(from, to, 1) // exited from, to := copyMem(from, to, 1) // exited
from, to := copyMem(from, to, 8) // step from, to := copyMem(from, to, 8) // step
from := add(from, 32) // offset to registers from := add(from, 32) // offset to registers
for { let i := 0 } lt(i, 32) { i := add(i, 1) } { from, to := copyMem(from, to, 4) } // registers
mstore(to, 0) // clean up end // Copy registers
log0(start, sub(to, start)) // log the resulting MIPS state, for debugging for { let i := 0 } lt(i, 32) { i := add(i, 1) } {
out := keccak256(start, sub(to, start)) from, to := copyMem(from, to, 4)
} }
return out;
// Clean up end of memory
mstore(to, 0)
// Log the resulting MIPS state, for debugging
log0(start, sub(to, start))
// Compute the hash of the resulting MIPS state
out_ := keccak256(start, sub(to, start))
}
return out_;
} }
/// @notice Handles a syscall.
function handleSyscall() internal returns (bytes32) { function handleSyscall() internal returns (bytes32) {
// Load state from memory
State memory state; State memory state;
assembly { assembly {
state := 0x80 state := 0x80
} }
uint32 syscall_no = state.registers[2]; uint32 syscall_no = state.registers[2];
uint32 v0 = 0; uint32 v0 = 0;
uint32 v1 = 0; uint32 v1 = 0;
...@@ -209,177 +232,313 @@ contract MIPS { ...@@ -209,177 +232,313 @@ contract MIPS {
return outputState(); return outputState();
} }
function handleBranch(uint32 opcode, uint32 insn, uint32 rtReg, uint32 rs) internal returns (bytes32) { /// @notice Handles a branch instruction, updating the MIPS state PC where needed.
/// @param _opcode The opcode of the branch instruction.
/// @param _insn The instruction to be executed.
/// @param _rtReg The register to be used for the branch.
/// @param _rs The register to be compared with the branch register.
/// @return out_ The hashed MIPS state.
function handleBranch(uint32 _opcode, uint32 _insn, uint32 _rtReg, uint32 _rs) internal returns (bytes32 out_) {
// Load state from memory
State memory state; State memory state;
assembly { assembly {
state := 0x80 state := 0x80
} }
bool shouldBranch = false; bool shouldBranch = false;
if (opcode == 4 || opcode == 5) { // beq/bne // beq/bne: Branch on equal / not equal
uint32 rt = state.registers[rtReg]; if (_opcode == 4 || _opcode == 5) {
shouldBranch = (rs == rt && opcode == 4) || (rs != rt && opcode == 5); uint32 rt = state.registers[_rtReg];
} else if (opcode == 6) { shouldBranch = int32(rs) <= 0; // blez shouldBranch = (_rs == rt && _opcode == 4) || (_rs != rt && _opcode == 5);
} else if (opcode == 7) { shouldBranch = int32(rs) > 0; // bgtz }
} else if (opcode == 1) { // blez: Branches if instruction is less than or equal to zero
else if (_opcode == 6) {
shouldBranch = int32(_rs) <= 0;
}
// bgtz: Branches if instruction is greater than zero
else if (_opcode == 7) {
shouldBranch = int32(_rs) > 0;
}
// bltz/bgez: Branch on less than zero / greater than or equal to zero
else if (_opcode == 1) {
// regimm // regimm
uint32 rtv = ((insn >> 16) & 0x1F); uint32 rtv = ((_insn >> 16) & 0x1F);
if (rtv == 0) shouldBranch = int32(rs) < 0; // bltz if (rtv == 0) {
if (rtv == 1) shouldBranch = int32(rs) >= 0; // bgez shouldBranch = int32(_rs) < 0;
}
if (rtv == 1) {
shouldBranch = int32(_rs) >= 0;
}
} }
// Update the state's previous PC
uint32 prevPC = state.pc; uint32 prevPC = state.pc;
state.pc = state.nextPC; // execute the delay slot first
// Execute the delay slot first
state.pc = state.nextPC;
// If we should branch, update the PC to the branch target
// Otherwise, proceed to the next instruction
if (shouldBranch) { if (shouldBranch) {
state.nextPC = prevPC + 4 + (SE(insn&0xFFFF, 16)<<2); // then continue with the instruction the branch jumps to. state.nextPC = prevPC + 4 + (SE(_insn & 0xFFFF, 16) << 2);
} else { } else {
state.nextPC = state.nextPC + 4; // branch not taken state.nextPC = state.nextPC + 4;
} }
return outputState(); // Return the hash of the resulting state
out_ = outputState();
} }
function handleHiLo(uint32 func, uint32 rs, uint32 rt, uint32 storeReg) internal returns (bytes32) { /// @notice Handles HI and LO register instructions.
/// @param _func The function code of the instruction.
/// @param _rs The value of the RS register.
/// @param _rt The value of the RT register.
/// @param _storeReg The register to store the result in.
/// @return out_ The hash of the resulting MIPS state.
function handleHiLo(uint32 _func, uint32 _rs, uint32 _rt, uint32 _storeReg) internal returns (bytes32 out_) {
// Load state from memory
State memory state; State memory state;
assembly { assembly {
state := 0x80 state := 0x80
} }
uint32 val; uint32 val;
if (func == 0x10) val = state.hi; // mfhi
else if (func == 0x11) state.hi = rs; // mthi // mfhi: Move the contents of the HI register into the destination
else if (func == 0x12) val = state.lo; // mflo if (_func == 0x10) {
else if (func == 0x13) state.lo = rs; // mtlo val = state.hi;
else if (func == 0x18) { // mult }
uint64 acc = uint64(int64(int32(rs))*int64(int32(rt))); // mthi: Move the contents of the source into the HI register
state.hi = uint32(acc>>32); else if (_func == 0x11) {
state.hi = _rs;
}
// mflo: Move the contents of the LO register into the destination
else if (_func == 0x12) {
val = state.lo;
}
// mtlo: Move the contents of the source into the LO register
else if (_func == 0x13) {
state.lo = _rs;
}
// mult: Multiplies `rs` by `rt` and stores the result in HI and LO registers
else if (_func == 0x18) {
uint64 acc = uint64(int64(int32(_rs)) * int64(int32(_rt)));
state.hi = uint32(acc >> 32);
state.lo = uint32(acc); state.lo = uint32(acc);
} else if (func == 0x19) { // multu }
uint64 acc = uint64(uint64(rs)*uint64(rt)); // multu: Unsigned multiplies `rs` by `rt` and stores the result in HI and LO registers
state.hi = uint32(acc>>32); else if (_func == 0x19) {
uint64 acc = uint64(uint64(_rs) * uint64(_rt));
state.hi = uint32(acc >> 32);
state.lo = uint32(acc); state.lo = uint32(acc);
} else if (func == 0x1a) { // div }
state.hi = uint32(int32(rs)%int32(rt)); // div: Divides `rs` by `rt`.
state.lo = uint32(int32(rs)/int32(rt)); // Stores the quotient in LO
} else if (func == 0x1b) { // divu // And the remainder in HI
state.hi = rs%rt; else if (_func == 0x1a) {
state.lo = rs/rt; state.hi = uint32(int32(_rs) % int32(_rt));
state.lo = uint32(int32(_rs) / int32(_rt));
}
// divu: Unsigned divides `rs` by `rt`.
// Stores the quotient in LO
// And the remainder in HI
else if (_func == 0x1b) {
state.hi = _rs % _rt;
state.lo = _rs / _rt;
} }
if (storeReg != 0) { // Store the result in the destination register, if applicable
state.registers[storeReg] = val; if (_storeReg != 0) {
state.registers[_storeReg] = val;
} }
// Update the PC
state.pc = state.nextPC; state.pc = state.nextPC;
state.nextPC = state.nextPC + 4; state.nextPC = state.nextPC + 4;
return outputState(); // Return the hash of the resulting state
out_ = outputState();
} }
function handleJump(uint32 linkReg, uint32 dest) internal returns (bytes32) { /// @notice Handles a jump instruction, updating the MIPS state PC where needed.
/// @param _linkReg The register to store the link to the instruction after the delay slot instruction.
/// @param _dest The destination to jump to.
/// @return out_ The hashed MIPS state.
function handleJump(uint32 _linkReg, uint32 _dest) internal returns (bytes32 out_) {
// Load state from memory.
State memory state; State memory state;
assembly { assembly {
state := 0x80 state := 0x80
} }
// Update the next PC to the jump destination.
uint32 prevPC = state.pc; uint32 prevPC = state.pc;
state.pc = state.nextPC; state.pc = state.nextPC;
state.nextPC = dest; state.nextPC = _dest;
if (linkReg != 0) {
state.registers[linkReg] = prevPC+8; // set the link-register to the instr after the delay slot instruction. // Update the link-register to the instruction after the delay slot instruction.
if (_linkReg != 0) {
state.registers[_linkReg] = prevPC + 8;
} }
return outputState();
// Return the hash of the resulting state.
out_ = outputState();
} }
function handleRd(uint32 storeReg, uint32 val, bool conditional) internal returns (bytes32) { /// @notice Handles a storing a value into a register.
/// @param _storeReg The register to store the value into.
/// @param _val The value to store.
/// @param _conditional Whether or not the store is conditional.
/// @return out_ The hashed MIPS state.
function handleRd(uint32 _storeReg, uint32 _val, bool _conditional) internal returns (bytes32 out_) {
// Load state from memory.
State memory state; State memory state;
assembly { assembly {
state := 0x80 state := 0x80
} }
require(storeReg < 32, "valid register");
// never write to reg 0, and it can be conditional (movz, movn) // The destination register must be valid.
if (storeReg != 0 && conditional) { require(_storeReg < 32, "valid register");
state.registers[storeReg] = val;
// Never write to reg 0, and it can be conditional (movz, movn).
if (_storeReg != 0 && _conditional) {
state.registers[_storeReg] = _val;
} }
// Update the PC.
state.pc = state.nextPC; state.pc = state.nextPC;
state.nextPC = state.nextPC + 4; state.nextPC = state.nextPC + 4;
return outputState(); // Return the hash of the resulting state.
out_ = outputState();
} }
function proofOffset(uint8 proofIndex) internal pure returns (uint256 offset) { /// @notice Computes the offset of the proof in the calldata.
/// @param _proofIndex The index of the proof in the calldata.
/// @return offset_ The offset of the proof in the calldata.
function proofOffset(uint8 _proofIndex) internal pure returns (uint256 offset_) {
// A proof of 32 bit memory, with 32-byte leaf values, is (32-5)=27 bytes32 entries. // A proof of 32 bit memory, with 32-byte leaf values, is (32-5)=27 bytes32 entries.
// And the leaf value itself needs to be encoded as well. And proof.offset == 358 // And the leaf value itself needs to be encoded as well. And proof.offset == 358
offset = 358 + (uint256(proofIndex) * (28*32)); offset_ = 358 + (uint256(_proofIndex) * (28 * 32));
uint256 s = 0; uint256 s = 0;
assembly { s := calldatasize() } assembly { s := calldatasize() }
require(s >= (offset + 28*32), "check that there is enough calldata"); require(s >= (offset_ + 28 * 32), "check that there is enough calldata");
return offset; return offset_;
} }
function readMem(uint32 addr, uint8 proofIndex) internal pure returns (uint32 out) { /// @notice Reads a 32-bit value from memory.
uint256 offset = proofOffset(proofIndex); /// @param _addr The address to read from.
/// @param _proofIndex The index of the proof in the calldata.
/// @return out_ The hashed MIPS state.
function readMem(uint32 _addr, uint8 _proofIndex) internal pure returns (uint32 out_) {
// Compute the offset of the proof in the calldata.
uint256 offset = proofOffset(_proofIndex);
assembly { assembly {
if and(addr, 3) { revert(0, 0) } // quick addr alignment check // Validate the address alignement.
if and(_addr, 3) {
revert(0, 0)
}
// Load the leaf value.
let leaf := calldataload(offset) let leaf := calldataload(offset)
offset := add(offset, 32) offset := add(offset, 32)
// Convenience function to hash two nodes together in scratch space.
function hashPair(a, b) -> h { function hashPair(a, b) -> h {
mstore(0, a) // use scratch space slots to hash the two nodes together mstore(0, a)
mstore(32, b) mstore(32, b)
h := keccak256(0, 64) h := keccak256(0, 64)
} }
let path := shr(5, addr)
let node := leaf // starting from the leaf node, work back up by combining with siblings, to reconstruct the root // Start with the leaf node.
// Work back up by combining with siblings, to reconstruct the root.
let path := shr(5, _addr)
let node := leaf
for { let i := 0 } lt(i, 27) { i := add(i, 1) } { for { let i := 0 } lt(i, 27) { i := add(i, 1) } {
let sibling := calldataload(offset) let sibling := calldataload(offset)
offset := add(offset, 32) offset := add(offset, 32)
switch and(shr(i, path), 1) switch and(shr(i, path), 1)
case 0 { node := hashPair(node, sibling) } case 0 {
case 1 { node := hashPair(sibling, node) } node := hashPair(node, sibling)
} case 1 {
node := hashPair(sibling, node)
} }
let memRoot := mload(0x80) // load memRoot, first field of state }
if iszero(eq(node, memRoot)) { // verify the root matches
// Load the memory root from the first field of state.
let memRoot := mload(0x80)
// Verify the root matches.
if iszero(eq(node, memRoot)) {
mstore(0, 0x0badf00d) mstore(0, 0x0badf00d)
revert(0, 32) revert(0, 32)
} }
// bits to shift = (32 - 4 - (addr % 32)) * 8
let shamt := shl(3, sub(sub(32, 4), and(addr, 31))) // Bits to shift = (32 - 4 - (addr % 32)) * 8
out := and(shr(shamt, leaf), 0xFFffFFff) let shamt := shl(3, sub(sub(32, 4), and(_addr, 31)))
out_ := and(shr(shamt, leaf), 0xFFffFFff)
} }
return out;
} }
// writeMem writes the value by first overwriting the part of the leaf, and then recomputing the memory merkle root. /// @notice Writes a 32-bit value to memory.
function writeMem(uint32 addr, uint8 proofIndex, uint32 value) internal pure { /// This function first overwrites the part of the leaf.
uint256 offset = proofOffset(proofIndex); /// Then it recomputes the memory merkle root.
/// @param _addr The address to write to.
/// @param _proofIndex The index of the proof in the calldata.
/// @param _val The value to write.
function writeMem(uint32 _addr, uint8 _proofIndex, uint32 _val) internal pure {
// Compute the offset of the proof in the calldata.
uint256 offset = proofOffset(_proofIndex);
assembly { assembly {
if and(addr, 3) { revert(0, 0) } // quick addr alignment check // Validate the address alignement.
if and(_addr, 3) {
revert(0, 0)
}
// Load the leaf value.
let leaf := calldataload(offset) let leaf := calldataload(offset)
let shamt := shl(3, sub(sub(32, 4), and(addr, 31))) let shamt := shl(3, sub(sub(32, 4), and(_addr, 31)))
// mask out 4 bytes, and OR in the value
leaf := or(and(leaf, not(shl(shamt, 0xFFffFFff))), shl(shamt, value)) // Mask out 4 bytes, and OR in the value
leaf := or(and(leaf, not(shl(shamt, 0xFFffFFff))), shl(shamt, _val))
offset := add(offset, 32) offset := add(offset, 32)
// Convenience function to hash two nodes together in scratch space.
function hashPair(a, b) -> h { function hashPair(a, b) -> h {
mstore(0, a) // use scratch space slots to hash the two nodes together mstore(0, a)
mstore(32, b) mstore(32, b)
h := keccak256(0, 64) h := keccak256(0, 64)
} }
let path := shr(5, addr)
let node := leaf // starting from the leaf node, work back up by combining with siblings, to reconstruct the root // Start with the leaf node.
// Work back up by combining with siblings, to reconstruct the root.
let path := shr(5, _addr)
let node := leaf
for { let i := 0 } lt(i, 27) { i := add(i, 1) } { for { let i := 0 } lt(i, 27) { i := add(i, 1) } {
let sibling := calldataload(offset) let sibling := calldataload(offset)
offset := add(offset, 32) offset := add(offset, 32)
switch and(shr(i, path), 1) switch and(shr(i, path), 1)
case 0 { node := hashPair(node, sibling) } case 0 {
case 1 { node := hashPair(sibling, node) } node := hashPair(node, sibling)
} case 1 {
node := hashPair(sibling, node)
}
} }
mstore(0x80, node) // store new memRoot, first field of state
// Store the new memory root in the first field of state.
mstore(0x80, node)
} }
} }
// will revert if any required input state is missing /// @notice Executes a single step of the vm.
/// Will revert if any required input state is missing.
function step(bytes calldata stateData, bytes calldata proof) public returns (bytes32) { function step(bytes calldata stateData, bytes calldata proof) public returns (bytes32) {
State memory state; State memory state;
// packed data is ~6 times smaller
// Packed calldata is ~6 times smaller than state size
assembly { assembly {
if iszero(eq(state, 0x80)) { // expected state mem offset check if iszero(eq(state, 0x80)) { // expected state mem offset check
revert(0,0) revert(0,0)
...@@ -393,6 +552,7 @@ contract MIPS { ...@@ -393,6 +552,7 @@ contract MIPS {
if iszero(eq(proof.offset, 358)) { // 100+32+226=358 expected proof offset if iszero(eq(proof.offset, 358)) { // 100+32+226=358 expected proof offset
revert(0,0) revert(0,0)
} }
function putField(callOffset, memOffset, size) -> callOffsetOut, memOffsetOut { function putField(callOffset, memOffset, size) -> callOffsetOut, memOffsetOut {
// calldata is packed, thus starting left-aligned, shift-right to pad and right-align // calldata is packed, thus starting left-aligned, shift-right to pad and right-align
let w := shr(shl(3, sub(32, size)), calldataload(callOffset)) let w := shr(shl(3, sub(32, size)), calldataload(callOffset))
...@@ -400,6 +560,8 @@ contract MIPS { ...@@ -400,6 +560,8 @@ contract MIPS {
callOffsetOut := add(callOffset, size) callOffsetOut := add(callOffset, size)
memOffsetOut := add(memOffset, 32) memOffsetOut := add(memOffset, 32)
} }
// Unpack state from calldata into memory
let c := stateData.offset // calldata offset let c := stateData.offset // calldata offset
let m := 0x80 // mem offset let m := 0x80 // mem offset
c, m := putField(c, m, 32) // memRoot c, m := putField(c, m, 32) // memRoot
...@@ -413,25 +575,31 @@ contract MIPS { ...@@ -413,25 +575,31 @@ contract MIPS {
c, m := putField(c, m, 1) // exitCode c, m := putField(c, m, 1) // exitCode
c, m := putField(c, m, 1) // exited c, m := putField(c, m, 1) // exited
c, m := putField(c, m, 8) // step c, m := putField(c, m, 8) // step
// Unpack register calldata into memory
mstore(m, add(m, 32)) // offset to registers mstore(m, add(m, 32)) // offset to registers
m := add(m, 32) m := add(m, 32)
for { let i := 0 } lt(i, 32) { i := add(i, 1) } { c, m := putField(c, m, 4) } // registers for { let i := 0 } lt(i, 32) { i := add(i, 1) } {
c, m := putField(c, m, 4)
} }
if(state.exited) { // don't change state once exited }
// Don't change state once exited
if (state.exited) {
return outputState(); return outputState();
} }
state.step += 1; state.step += 1;
// instruction fetch // instruction fetch
uint32 insn = readMem(state.pc, 0); uint32 insn = readMem(state.pc, 0);
uint32 opcode = insn >> 26; // 6-bits uint32 opcode = insn >> 26; // 6-bits
// j-type j/jal // j-type j/jal
if (opcode == 2 || opcode == 3) { if (opcode == 2 || opcode == 3) {
// TODO(CLI-4136): likely bug in original code: MIPS spec says this should be in the "current" region; // TODO(CLI-4136): likely bug in original code: MIPS spec says this should be in the "current" region;
// a 256 MB aligned region (i.e. use top 4 bits of branch delay slot (pc+4)) // a 256 MB aligned region (i.e. use top 4 bits of branch delay slot (pc+4))
return handleJump(opcode == 2 ? 0 : 31, SE(insn&0x03FFFFFF, 26) << 2); return handleJump(opcode == 2 ? 0 : 31, SE(insn & 0x03FFFFFF, 26) << 2);
} }
// register fetch // register fetch
...@@ -442,6 +610,7 @@ contract MIPS { ...@@ -442,6 +610,7 @@ contract MIPS {
// R-type or I-type (stores rt) // R-type or I-type (stores rt)
rs = state.registers[(insn >> 21) & 0x1F]; rs = state.registers[(insn >> 21) & 0x1F];
uint32 rdReg = rtReg; uint32 rdReg = rtReg;
if (opcode == 0 || opcode == 0x1c) { if (opcode == 0 || opcode == 0x1c) {
// R-type (stores rd) // R-type (stores rd)
rt = state.registers[rtReg]; rt = state.registers[rtReg];
...@@ -451,10 +620,10 @@ contract MIPS { ...@@ -451,10 +620,10 @@ contract MIPS {
// don't sign extend for andi, ori, xori // don't sign extend for andi, ori, xori
if (opcode == 0xC || opcode == 0xD || opcode == 0xe) { if (opcode == 0xC || opcode == 0xD || opcode == 0xe) {
// ZeroExtImm // ZeroExtImm
rt = insn&0xFFFF; rt = insn & 0xFFFF;
} else { } else {
// SignExtImm // SignExtImm
rt = SE(insn&0xFFFF, 16); rt = SE(insn & 0xFFFF, 16);
} }
} else if (opcode >= 0x28 || opcode == 0x22 || opcode == 0x26) { } else if (opcode >= 0x28 || opcode == 0x22 || opcode == 0x26) {
// store rt value with store // store rt value with store
...@@ -527,6 +696,7 @@ contract MIPS { ...@@ -527,6 +696,7 @@ contract MIPS {
return handleRd(rdReg, val, true); return handleRd(rdReg, val, true);
} }
/// @notice Execute an instruction.
function execute(uint32 insn, uint32 rs, uint32 rt, uint32 mem) internal pure returns (uint32) { function execute(uint32 insn, uint32 rs, uint32 rt, uint32 mem) internal pure returns (uint32) {
uint32 opcode = insn >> 26; // 6-bits uint32 opcode = insn >> 26; // 6-bits
uint32 func = insn & 0x3f; // 6-bits uint32 func = insn & 0x3f; // 6-bits
...@@ -550,76 +720,164 @@ contract MIPS { ...@@ -550,76 +720,164 @@ contract MIPS {
if (opcode == 0) { if (opcode == 0) {
uint32 shamt = (insn >> 6) & 0x1f; uint32 shamt = (insn >> 6) & 0x1f;
if (func < 0x20) { if (func < 0x20) {
if (func >= 0x08) { return rs; // jr/jalr/div + others // jr/jalr/div + others
// Shift and ShiftV if (func >= 0x08) {
} else if (func == 0x00) { return rt << shamt; // sll return rs;
} else if (func == 0x02) { return rt >> shamt; // srl
} else if (func == 0x03) { return SE(rt >> shamt, 32-shamt); // sra
} else if (func == 0x04) { return rt << (rs&0x1F); // sllv
} else if (func == 0x06) { return rt >> (rs&0x1F); // srlv
} else if (func == 0x07) { return SE(rt >> rs, 32-rs); // srav
} }
// sll: Logical Shift Left
else if (func == 0x00) {
return rt << shamt;
} }
// 0x10-0x13 = mfhi, mthi, mflo, mtlo // srl: Logical Shift Right
else if (func == 0x02) {
return rt >> shamt;
}
// sra: Arithmetic Shift Right
else if (func == 0x03) {
return SE(rt >> shamt, 32 - shamt);
}
// sllv: Variable Logical Shift Left
else if (func == 0x04) {
return rt << (rs & 0x1F);
}
// srlv: Variable Logical Shift Right
else if (func == 0x06) {
return rt >> (rs & 0x1F);
}
// srav: Variable Arithmetic Shift Right
else if (func == 0x07) {
return SE(rt >> rs, 32 - rs);
}
}
// R-type (ArithLog) // R-type (ArithLog)
if (func == 0x20 || func == 0x21) { return rs+rt; // add or addu // 0x10-0x13 = mfhi, mthi, mflo, mtlo
} else if (func == 0x22 || func == 0x23) { return rs-rt; // sub or subu // add or addu
} else if (func == 0x24) { return rs&rt; // and if (func == 0x20 || func == 0x21) {
} else if (func == 0x25) { return (rs|rt); // or return rs + rt;
} else if (func == 0x26) { return (rs^rt); // xor }
} else if (func == 0x27) { return ~(rs|rt); // nor // sub or subu
} else if (func == 0x2a) { else if (func == 0x22 || func == 0x23) {
return int32(rs)<int32(rt) ? 1 : 0; // slt return rs - rt;
} else if (func == 0x2B) { }
return rs<rt ? 1 : 0; // sltu // and
} else if (func == 0x24) {
} else if (opcode == 0xf) { return rt<<16; // lui return rs & rt;
} else if (opcode == 0x1c) { // SPECIAL2 }
if (func == 2) return uint32(int32(rs)*int32(rt)); // mul // or
if (func == 0x20 || func == 0x21) { // clo else if (func == 0x25) {
if (func == 0x20) rs = ~rs; return (rs | rt);
uint32 i = 0; while (rs&0x80000000 != 0) { i++; rs <<= 1; } return i; }
} // xor
} else if (func == 0x26) {
} else if (opcode < 0x28) { return (rs ^ rt);
if (opcode == 0x20) { // lb }
return SE((mem >> (24-(rs&3)*8)) & 0xFF, 8); // nor
} else if (opcode == 0x21) { // lh else if (func == 0x27) {
return SE((mem >> (16-(rs&2)*8)) & 0xFFFF, 16); return ~(rs | rt);
} else if (opcode == 0x22) { // lwl }
uint32 val = mem << ((rs&3)*8); // slt: Set to 1 if less than
uint32 mask = uint32(0xFFFFFFFF) << ((rs&3)*8); else if (func == 0x2a) {
return int32(rs) < int32(rt) ? 1 : 0;
}
// sltu: Set to 1 if less than unsigned
else if (func == 0x2B) {
return rs<rt ? 1 : 0;
}
}
// lui: Load Upper Immediate
else if (opcode == 0xf) {
return rt << 16;
}
// SPECIAL2
else if (opcode == 0x1c) {
// mul
if (func == 2) {
return uint32(int32(rs) * int32(rt));
}
// clo
if (func == 0x20 || func == 0x21) {
if (func == 0x20) {
rs = ~rs;
}
uint32 i = 0;
while (rs&0x80000000 != 0) {
i++;
rs <<= 1;
}
return i;
}
}
}
else if (opcode < 0x28) {
// lb
if (opcode == 0x20) {
return SE((mem >> (24 - (rs & 3) * 8)) & 0xFF, 8);
}
// lh
else if (opcode == 0x21) {
return SE((mem >> (16 - (rs & 2) * 8)) & 0xFFFF, 16);
}
// lwl
else if (opcode == 0x22) {
uint32 val = mem << ((rs & 3) * 8);
uint32 mask = uint32(0xFFFFFFFF) << ((rs & 3) * 8);
return (rt & ~mask) | val; return (rt & ~mask) | val;
} else if (opcode == 0x23) { return mem; // lw }
} else if (opcode == 0x24) { // lbu // lw
return (mem >> (24-(rs&3)*8)) & 0xFF; else if (opcode == 0x23) {
} else if (opcode == 0x25) { // lhu return mem;
return (mem >> (16-(rs&2)*8)) & 0xFFFF; }
} else if (opcode == 0x26) { // lwr // lbu
uint32 val = mem >> (24-(rs&3)*8); else if (opcode == 0x24) {
uint32 mask = uint32(0xFFFFFFFF) >> (24-(rs&3)*8); return (mem >> (24 - (rs & 3) * 8)) & 0xFF;
}
// lhu
else if (opcode == 0x25) {
return (mem >> (16 - (rs & 2) * 8)) & 0xFFFF;
}
// lwr
else if (opcode == 0x26) {
uint32 val = mem >> (24 - (rs & 3) * 8);
uint32 mask = uint32(0xFFFFFFFF) >> (24 - (rs & 3) * 8);
return (rt & ~mask) | val; return (rt & ~mask) | val;
} }
} else if (opcode == 0x28) { // sb }
uint32 val = (rt&0xFF) << (24-(rs&3)*8); // sb
uint32 mask = 0xFFFFFFFF ^ uint32(0xFF << (24-(rs&3)*8)); else if (opcode == 0x28) {
uint32 val = (rt & 0xFF) << (24 - (rs & 3) * 8);
uint32 mask = 0xFFFFFFFF ^ uint32(0xFF << (24 - (rs & 3) * 8));
return (mem & mask) | val; return (mem & mask) | val;
} else if (opcode == 0x29) { // sh }
uint32 val = (rt&0xFFFF) << (16-(rs&2)*8); // sh
uint32 mask = 0xFFFFFFFF ^ uint32(0xFFFF << (16-(rs&2)*8)); else if (opcode == 0x29) {
uint32 val = (rt & 0xFFFF) << (16 - (rs & 2) * 8);
uint32 mask = 0xFFFFFFFF ^ uint32(0xFFFF << (16 - (rs & 2) * 8));
return (mem & mask) | val; return (mem & mask) | val;
} else if (opcode == 0x2a) { // swl }
uint32 val = rt >> ((rs&3)*8); // swl
uint32 mask = uint32(0xFFFFFFFF) >> ((rs&3)*8); else if (opcode == 0x2a) {
uint32 val = rt >> ((rs & 3) * 8);
uint32 mask = uint32(0xFFFFFFFF) >> ((rs & 3) * 8);
return (mem & ~mask) | val; return (mem & ~mask) | val;
} else if (opcode == 0x2b) { // sw }
// sw
else if (opcode == 0x2b) {
return rt; return rt;
} else if (opcode == 0x2e) { // swr }
uint32 val = rt << (24-(rs&3)*8); // swr
uint32 mask = uint32(0xFFFFFFFF) << (24-(rs&3)*8); else if (opcode == 0x2e) {
uint32 val = rt << (24 - (rs & 3) * 8);
uint32 mask = uint32(0xFFFFFFFF) << (24 - (rs & 3) * 8);
return (mem & ~mask) | val; return (mem & ~mask) | val;
} else if (opcode == 0x30) { return mem; // ll }
} else if (opcode == 0x38) { return rt; // sc // ll
else if (opcode == 0x30) {
return mem;
}
// sc
else if (opcode == 0x38) {
return rt;
} }
revert("invalid instruction"); revert("invalid instruction");
......
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