Existing implementation of SRAV had a bug where it would perform a
shift with all bytes of the rs register when the spec says it
should only be using the lower 5 bits of the register. Updates the
implementation to reflect this, updates the existing test to use
the same test vector as provided in the open mips tests, and adds
fuzz tests that shows srav works as expected with rs values that
have more than the lower 5 bits set.