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Commits
52783f02
Unverified
Commit
52783f02
authored
Oct 09, 2024
by
Chen Kai
Committed by
GitHub
Oct 08, 2024
Browse files
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Plain Diff
fix:fix load/store test compatible cannon64 (#12345)
Signed-off-by:
Chen Kai
<
281165273grape@gmail.com
>
parent
a05feb36
Changes
2
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2 changed files
with
27 additions
and
22 deletions
+27
-22
evm_common_test.go
cannon/mipsevm/tests/evm_common_test.go
+22
-22
state.go
cannon/mipsevm/testutil/state.go
+5
-0
No files found.
cannon/mipsevm/tests/evm_common_test.go
View file @
52783f02
...
@@ -248,31 +248,31 @@ func TestEVMSingleStep_LoadStore(t *testing.T) {
...
@@ -248,31 +248,31 @@ func TestEVMSingleStep_LoadStore(t *testing.T) {
versions
:=
GetMipsVersionTestCases
(
t
)
versions
:=
GetMipsVersionTestCases
(
t
)
cases
:=
[]
struct
{
cases
:=
[]
struct
{
name
string
name
string
rs
uint32
rs
Word
rt
uint32
rt
Word
isUnAligned
bool
isUnAligned
bool
opcode
uint32
opcode
uint32
memVal
uint32
memVal
Word
expectMemVal
uint32
expectMemVal
Word
expectRes
uint32
expectRes
Word
}{
}{
{
name
:
"lb"
,
opcode
:
uint32
(
0x20
),
memVal
:
uint32
(
0x12
_00_00_00
),
expectRes
:
uint32
(
0x12
)},
// lb $t0, 4($t1)
{
name
:
"lb"
,
opcode
:
uint32
(
0x20
),
memVal
:
Word
(
0x12
_00_00_00
),
expectRes
:
Word
(
0x12
)},
// lb $t0, 4($t1)
{
name
:
"lh"
,
opcode
:
uint32
(
0x21
),
memVal
:
uint32
(
0x12
_23_00_00
),
expectRes
:
uint32
(
0x12
_23
)},
// lh $t0, 4($t1)
{
name
:
"lh"
,
opcode
:
uint32
(
0x21
),
memVal
:
Word
(
0x12
_23_00_00
),
expectRes
:
Word
(
0x12
_23
)},
// lh $t0, 4($t1)
{
name
:
"lw"
,
opcode
:
uint32
(
0x23
),
memVal
:
uint32
(
0x12
_23_45_67
),
expectRes
:
uint32
(
0x12
_23_45_67
)},
// lw $t0, 4($t1)
{
name
:
"lw"
,
opcode
:
uint32
(
0x23
),
memVal
:
Word
(
0x12
_23_45_67
),
expectRes
:
Word
(
0x12
_23_45_67
)},
// lw $t0, 4($t1)
{
name
:
"lbu"
,
opcode
:
uint32
(
0x24
),
memVal
:
uint32
(
0x12
_23_00_00
),
expectRes
:
uint32
(
0x12
)},
// lbu $t0, 4($t1)
{
name
:
"lbu"
,
opcode
:
uint32
(
0x24
),
memVal
:
Word
(
0x12
_23_00_00
),
expectRes
:
Word
(
0x12
)},
// lbu $t0, 4($t1)
{
name
:
"lhu"
,
opcode
:
uint32
(
0x25
),
memVal
:
uint32
(
0x12
_23_00_00
),
expectRes
:
uint32
(
0x12
_23
)},
// lhu $t0, 4($t1)
{
name
:
"lhu"
,
opcode
:
uint32
(
0x25
),
memVal
:
Word
(
0x12
_23_00_00
),
expectRes
:
Word
(
0x12
_23
)},
// lhu $t0, 4($t1)
{
name
:
"lwl"
,
opcode
:
uint32
(
0x22
),
rt
:
uint32
(
0xaa
_bb_cc_dd
),
memVal
:
uint32
(
0x12
_34_56_78
),
expectRes
:
uint32
(
0x12
_34_56_78
)},
// lwl $t0, 4($t1)
{
name
:
"lwl"
,
opcode
:
uint32
(
0x22
),
rt
:
Word
(
0xaa
_bb_cc_dd
),
memVal
:
Word
(
0x12
_34_56_78
),
expectRes
:
Word
(
0x12
_34_56_78
)},
// lwl $t0, 4($t1)
{
name
:
"lwl unaligned address"
,
opcode
:
uint32
(
0x22
),
rt
:
uint32
(
0xaa
_bb_cc_dd
),
isUnAligned
:
true
,
memVal
:
uint32
(
0x12
_34_56_78
),
expectRes
:
uint32
(
0x34
_56_78_dd
)},
// lwl $t0, 5($t1)
{
name
:
"lwl unaligned address"
,
opcode
:
uint32
(
0x22
),
rt
:
Word
(
0xaa
_bb_cc_dd
),
isUnAligned
:
true
,
memVal
:
Word
(
0x12
_34_56_78
),
expectRes
:
Word
(
0x34
_56_78_dd
)},
// lwl $t0, 5($t1)
{
name
:
"lwr"
,
opcode
:
uint32
(
0x26
),
rt
:
uint32
(
0xaa
_bb_cc_dd
),
memVal
:
uint32
(
0x12
_34_56_78
),
expectRes
:
uint32
(
0xaa
_bb_cc_12
)},
// lwr $t0, 4($t1)
{
name
:
"lwr"
,
opcode
:
uint32
(
0x26
),
rt
:
Word
(
0xaa
_bb_cc_dd
),
memVal
:
Word
(
0x12
_34_56_78
),
expectRes
:
Word
(
0xaa
_bb_cc_12
)},
// lwr $t0, 4($t1)
{
name
:
"lwr unaligned address"
,
opcode
:
uint32
(
0x26
),
rt
:
uint32
(
0xaa
_bb_cc_dd
),
isUnAligned
:
true
,
memVal
:
uint32
(
0x12
_34_56_78
),
expectRes
:
uint32
(
0xaa
_bb_12_34
)},
// lwr $t0, 5($t1)
{
name
:
"lwr unaligned address"
,
opcode
:
uint32
(
0x26
),
rt
:
Word
(
0xaa
_bb_cc_dd
),
isUnAligned
:
true
,
memVal
:
Word
(
0x12
_34_56_78
),
expectRes
:
Word
(
0xaa
_bb_12_34
)},
// lwr $t0, 5($t1)
{
name
:
"sb"
,
opcode
:
uint32
(
0x28
),
rt
:
uint32
(
0xaa
_bb_cc_dd
),
expectMemVal
:
uint32
(
0xdd
_00_00_00
)},
// sb $t0, 4($t1)
{
name
:
"sb"
,
opcode
:
uint32
(
0x28
),
rt
:
Word
(
0xaa
_bb_cc_dd
),
expectMemVal
:
Word
(
0xdd
_00_00_00
)},
// sb $t0, 4($t1)
{
name
:
"sh"
,
opcode
:
uint32
(
0x29
),
rt
:
uint32
(
0xaa
_bb_cc_dd
),
expectMemVal
:
uint32
(
0xcc
_dd_00_00
)},
// sh $t0, 4($t1)
{
name
:
"sh"
,
opcode
:
uint32
(
0x29
),
rt
:
Word
(
0xaa
_bb_cc_dd
),
expectMemVal
:
Word
(
0xcc
_dd_00_00
)},
// sh $t0, 4($t1)
{
name
:
"swl"
,
opcode
:
uint32
(
0x2a
),
rt
:
uint32
(
0xaa
_bb_cc_dd
),
expectMemVal
:
uint32
(
0xaa
_bb_cc_dd
)},
// swl $t0, 4($t1)
{
name
:
"swl"
,
opcode
:
uint32
(
0x2a
),
rt
:
Word
(
0xaa
_bb_cc_dd
),
expectMemVal
:
Word
(
0xaa
_bb_cc_dd
)},
// swl $t0, 4($t1)
{
name
:
"sw"
,
opcode
:
uint32
(
0x2b
),
rt
:
uint32
(
0xaa
_bb_cc_dd
),
expectMemVal
:
uint32
(
0xaa
_bb_cc_dd
)},
// sw $t0, 4($t1)
{
name
:
"sw"
,
opcode
:
uint32
(
0x2b
),
rt
:
Word
(
0xaa
_bb_cc_dd
),
expectMemVal
:
Word
(
0xaa
_bb_cc_dd
)},
// sw $t0, 4($t1)
{
name
:
"swr unaligned address"
,
opcode
:
uint32
(
0x2e
),
rt
:
uint32
(
0xaa
_bb_cc_dd
),
isUnAligned
:
true
,
expectMemVal
:
uint32
(
0xcc
_dd_00_00
)},
// swr $t0, 5($t1)
{
name
:
"swr unaligned address"
,
opcode
:
uint32
(
0x2e
),
rt
:
Word
(
0xaa
_bb_cc_dd
),
isUnAligned
:
true
,
expectMemVal
:
Word
(
0xcc
_dd_00_00
)},
// swr $t0, 5($t1)
}
}
var
t1
uint32
=
0x100
var
t1
Word
=
0x100
var
baseReg
uint32
=
9
var
baseReg
uint32
=
9
var
rtReg
uint32
=
8
var
rtReg
uint32
=
8
for
_
,
v
:=
range
versions
{
for
_
,
v
:=
range
versions
{
...
@@ -292,7 +292,7 @@ func TestEVMSingleStep_LoadStore(t *testing.T) {
...
@@ -292,7 +292,7 @@ func TestEVMSingleStep_LoadStore(t *testing.T) {
state
.
GetRegistersRef
()[
baseReg
]
=
t1
state
.
GetRegistersRef
()[
baseReg
]
=
t1
state
.
GetMemory
()
.
SetUint32
(
0
,
insn
)
state
.
GetMemory
()
.
SetUint32
(
0
,
insn
)
state
.
GetMemory
()
.
Set
Uint32
(
t1
+
4
,
tt
.
memVal
)
state
.
GetMemory
()
.
Set
Word
(
t1
+
4
,
tt
.
memVal
)
step
:=
state
.
GetStep
()
step
:=
state
.
GetStep
()
// Setup expectations
// Setup expectations
...
@@ -300,7 +300,7 @@ func TestEVMSingleStep_LoadStore(t *testing.T) {
...
@@ -300,7 +300,7 @@ func TestEVMSingleStep_LoadStore(t *testing.T) {
expected
.
ExpectStep
()
expected
.
ExpectStep
()
if
tt
.
expectMemVal
!=
0
{
if
tt
.
expectMemVal
!=
0
{
expected
.
ExpectMemoryWrite
(
t1
+
4
,
tt
.
expectMemVal
)
expected
.
ExpectMemoryWrite
Word
(
t1
+
4
,
tt
.
expectMemVal
)
}
else
{
}
else
{
expected
.
Registers
[
rtReg
]
=
tt
.
expectRes
expected
.
Registers
[
rtReg
]
=
tt
.
expectRes
}
}
...
...
cannon/mipsevm/testutil/state.go
View file @
52783f02
...
@@ -170,6 +170,11 @@ func (e *ExpectedState) ExpectMemoryWrite(addr arch.Word, val uint32) {
...
@@ -170,6 +170,11 @@ func (e *ExpectedState) ExpectMemoryWrite(addr arch.Word, val uint32) {
e
.
MemoryRoot
=
e
.
expectedMemory
.
MerkleRoot
()
e
.
MemoryRoot
=
e
.
expectedMemory
.
MerkleRoot
()
}
}
func
(
e
*
ExpectedState
)
ExpectMemoryWriteWord
(
addr
arch
.
Word
,
val
arch
.
Word
)
{
e
.
expectedMemory
.
SetWord
(
addr
,
val
)
e
.
MemoryRoot
=
e
.
expectedMemory
.
MerkleRoot
()
}
func
(
e
*
ExpectedState
)
Validate
(
t
testing
.
TB
,
actualState
mipsevm
.
FPVMState
)
{
func
(
e
*
ExpectedState
)
Validate
(
t
testing
.
TB
,
actualState
mipsevm
.
FPVMState
)
{
require
.
Equal
(
t
,
e
.
PreimageKey
,
actualState
.
GetPreimageKey
(),
fmt
.
Sprintf
(
"Expect preimageKey = %v"
,
e
.
PreimageKey
))
require
.
Equal
(
t
,
e
.
PreimageKey
,
actualState
.
GetPreimageKey
(),
fmt
.
Sprintf
(
"Expect preimageKey = %v"
,
e
.
PreimageKey
))
require
.
Equal
(
t
,
e
.
PreimageOffset
,
actualState
.
GetPreimageOffset
(),
fmt
.
Sprintf
(
"Expect preimageOffset = %v"
,
e
.
PreimageOffset
))
require
.
Equal
(
t
,
e
.
PreimageOffset
,
actualState
.
GetPreimageOffset
(),
fmt
.
Sprintf
(
"Expect preimageOffset = %v"
,
e
.
PreimageOffset
))
...
...
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